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Date:   Thu, 3 Nov 2022 18:09:16 +0000
From:   Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To:     Davidlohr Bueso <dave@stgolabs.net>
CC:     Ira Weiny <ira.weiny@intel.com>,
        Bjorn Helgaas <helgaas@kernel.org>,
        "Dan Williams" <dan.j.williams@intel.com>, <dave.jiang@intel.com>,
        <alison.schofield@intel.com>, <bwidawsk@kernel.org>,
        <vishal.l.verma@intel.com>, <a.manzanares@samsung.com>,
        <linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        <linux-pci@vger.kernel.org>, Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support
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In-Reply-To: <20221103001833.n2gsoflnji3pcsfr@offworld>
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On Wed, 2 Nov 2022 17:18:33 -0700
Davidlohr Bueso <dave@stgolabs.net> wrote:

> On Wed, 02 Nov 2022, Ira Weiny wrote:
> 
> >On Wed, Nov 02, 2022 at 10:15:24AM -0700, Davidlohr Bueso wrote:  
> >> Most CXL features that can have irqs will normally use only the first 16,
> >> with the exception of isolation (cxl 3.0), which per the spec is up to 32.  
> >
> >Dan, Dave, and I were discussing this and we agree.  For now the only things
> >people are working on are within the first 16 so why not just request 16 as the
> >max for now?  
> 
> It is a fair compromise, yes.

works for me.