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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x5-20020a654145000000b0046ec0715bd9si4531909pgp.818.2022.11.04.04.03.27; Fri, 04 Nov 2022 04:03:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linux.microsoft.com header.s=default header.b=LcyRZOZT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linux.microsoft.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231565AbiKDKuB (ORCPT + 97 others); Fri, 4 Nov 2022 06:50:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229489AbiKDKt7 (ORCPT ); Fri, 4 Nov 2022 06:49:59 -0400 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6A9A62B24C; Fri, 4 Nov 2022 03:49:58 -0700 (PDT) Received: from anrayabh-desk (unknown [167.220.238.193]) by linux.microsoft.com (Postfix) with ESMTPSA id A4CC220B929B; Fri, 4 Nov 2022 03:49:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A4CC220B929B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1667558998; bh=2xtFBcRWDWUgb1O5tv1Wxinj7VDOrkrvZo9nr2w/dWw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=LcyRZOZT4uwhubWfNY1avDSNnScQlJOXFoRMziEB1j/gVVHrJdwPuKSLC35L6tIh4 C6LHoMDparOAnaHiW0zZ/ytXBSS1W1t7YcJPbWbN9sKJWEHNnn3Ic9jBrffLyTyAwL pcXHcCq4h0h6nE8uRmOcD5U/zcbaQt1eQSyUZETk= Date: Fri, 4 Nov 2022 16:19:48 +0530 From: Anirudh Rayabharam To: Jinank Jain Cc: jinankjain@microsoft.com, kys@microsoft.com, haiyangz@microsoft.com, wei.liu@kernel.org, decui@microsoft.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, arnd@arndb.de, peterz@infradead.org, jpoimboe@kernel.org, seanjc@google.com, kirill.shutemov@linux.intel.com, ak@linux.intel.com, sathyanarayanan.kuppuswamy@linux.intel.com, linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, mikelley@microsoft.com Subject: Re: [PATCH v3 3/5] x86/hyperv: Add an interface to do nested hypercalls Message-ID: References: <10fdfe01578e691e4815e3427e09e64b45c4af58.1667480257.git.jinankjain@linux.microsoft.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <10fdfe01578e691e4815e3427e09e64b45c4af58.1667480257.git.jinankjain@linux.microsoft.com> X-Spam-Status: No, score=-19.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,ENV_AND_HDR_SPF_MATCH,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS,USER_IN_DEF_DKIM_WL,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 03, 2022 at 01:04:05PM +0000, Jinank Jain wrote: > According to TLFS, in order to communicate to L0 hypervisor there needs > to be an additional bit set in the control register. This communication > is required to perform priviledged instructions which can only be > performed by L0 hypervisor. An example of that could be setting up the > VMBus infrastructure. > > Signed-off-by: Jinank Jain > --- > arch/x86/include/asm/hyperv-tlfs.h | 3 ++- > arch/x86/include/asm/mshyperv.h | 42 +++++++++++++++++++++++++++--- > include/asm-generic/hyperv-tlfs.h | 1 + > 3 files changed, 41 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h > index 0319091e2019..fd066226f12b 100644 > --- a/arch/x86/include/asm/hyperv-tlfs.h > +++ b/arch/x86/include/asm/hyperv-tlfs.h > @@ -380,7 +380,8 @@ struct hv_nested_enlightenments_control { > __u32 reserved:31; > } features; > struct { > - __u32 reserved; > + __u32 inter_partition_comm:1; > + __u32 reserved:31; > } hypercallControls; > } __packed; > > diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h > index b0f16d06a0c5..32f6bed68e88 100644 > --- a/arch/x86/include/asm/mshyperv.h > +++ b/arch/x86/include/asm/mshyperv.h > @@ -76,10 +76,16 @@ static inline u64 hv_do_hypercall(u64 control, void *input, void *output) > return hv_status; > } > > +/* Hypercall to the L0 hypervisor */ > +static inline u64 hv_do_nested_hypercall(u64 control, void *input, void *output) > +{ > + return hv_do_hypercall(control | HV_HYPERCALL_NESTED, input, output); > +} > + > /* Fast hypercall with 8 bytes of input and no output */ > -static inline u64 hv_do_fast_hypercall8(u16 code, u64 input1) > +static inline u64 _hv_do_fast_hypercall8(u64 control, u16 code, u64 input1) > { > - u64 hv_status, control = (u64)code | HV_HYPERCALL_FAST_BIT; > + u64 hv_status; > > #ifdef CONFIG_X86_64 > { > @@ -107,10 +113,24 @@ static inline u64 hv_do_fast_hypercall8(u16 code, u64 input1) > return hv_status; > } > > +static inline u64 hv_do_fast_hypercall8(u16 code, u64 input1) > +{ > + u64 control = (u64)code | HV_HYPERCALL_FAST_BIT; > + > + return _hv_do_fast_hypercall8(control, code, input1); > +} > + > +static inline u64 hv_do_fast_nested_hypercall8(u16 code, u64 input1) > +{ > + u64 control = (u64)code | HV_HYPERCALL_FAST_BIT | HV_HYPERCALL_NESTED; > + > + return _hv_do_fast_hypercall8(control, code, input1); > +} > + > /* Fast hypercall with 16 bytes of input */ > -static inline u64 hv_do_fast_hypercall16(u16 code, u64 input1, u64 input2) > +static inline u64 _hv_do_fast_hypercall16(u64 control, u16 code, u64 input1, u64 input2) > { > - u64 hv_status, control = (u64)code | HV_HYPERCALL_FAST_BIT; > + u64 hv_status; > > #ifdef CONFIG_X86_64 > { > @@ -141,6 +161,20 @@ static inline u64 hv_do_fast_hypercall16(u16 code, u64 input1, u64 input2) > return hv_status; > } > > +static inline u64 hv_do_fast_hypercall16(u16 code, u64 input1, u64 input2) > +{ > + u64 control = (u64)code | HV_HYPERCALL_FAST_BIT; > + > + return _hv_do_fast_hypercall16(control, code, input1, input2); > +} > + > +static inline u64 hv_do_fast_nested_hypercall16(u16 code, u64 input1, u64 input2) > +{ > + u64 control = (u64)code | HV_HYPERCALL_FAST_BIT | HV_HYPERCALL_NESTED; > + > + return _hv_do_fast_hypercall16(control, code, input1, input2); > +} > + > extern struct hv_vp_assist_page **hv_vp_assist_page; > > static inline struct hv_vp_assist_page *hv_get_vp_assist_page(unsigned int cpu) > diff --git a/include/asm-generic/hyperv-tlfs.h b/include/asm-generic/hyperv-tlfs.h > index fdce7a4cfc6f..3840958201cd 100644 > --- a/include/asm-generic/hyperv-tlfs.h > +++ b/include/asm-generic/hyperv-tlfs.h > @@ -185,6 +185,7 @@ enum HV_GENERIC_SET_FORMAT { > #define HV_HYPERCALL_VARHEAD_OFFSET 17 > #define HV_HYPERCALL_VARHEAD_MASK GENMASK_ULL(26, 17) > #define HV_HYPERCALL_RSVD0_MASK GENMASK_ULL(31, 27) > +#define HV_HYPERCALL_NESTED BIT_ULL(31) > #define HV_HYPERCALL_REP_COMP_OFFSET 32 > #define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32) > #define HV_HYPERCALL_REP_COMP_MASK GENMASK_ULL(43, 32) > -- > 2.25.1 Reviewed-by: