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Date:   Fri, 04 Nov 2022 14:31:20 +0000
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v2 56/65] clk: ingenic: cgu: Switch to determine_rate
To:     Maxime Ripard <maxime@cerno.tech>
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Hi Maxime,

Le ven. 4 nov. 2022 =E0 14:18:13 +0100, Maxime Ripard=20
<maxime@cerno.tech> a =E9crit :
> The Ingenic CGU clocks implements a mux with a set_parent hook, but
> doesn't provide a determine_rate implementation.
>=20
> This is a bit odd, since set_parent() is there to, as its name=20
> implies,
> change the parent of a clock. However, the most likely candidate to
> trigger that parent change is a call to clk_set_rate(), with
> determine_rate() figuring out which parent is the best suited for a
> given rate.
>=20
> The other trigger would be a call to clk_set_parent(), but it's far=20
> less
> used, and it doesn't look like there's any obvious user for that=20
> clock.
>=20
> So, the set_parent hook is effectively unused, possibly because of an
> oversight. However, it could also be an explicit decision by the
> original author to avoid any reparenting but through an explicit call=20
> to
> clk_set_parent().
>=20
> The driver does implement round_rate() though, which means that we can
> change the rate of the clock, but we will never get to change the
> parent.
>=20
> However, It's hard to tell whether it's been done on purpose or not.
>=20
> Since we'll start mandating a determine_rate() implementation, let's
> convert the round_rate() implementation to a determine_rate(), which
> will also make the current behavior explicit. And if it was an
> oversight, the clock behaviour can be adjusted later on.

So it's partly on purpose, partly because I didn't know about=20
.determine_rate.

There's nothing odd about having a lonely .set_parent callback; in my=20
case the clocks are parented from the device tree.

Having the clocks driver trigger a parent change when requesting a rate=20
change sounds very dangerous, IMHO. My MMC controller can be parented=20
to the external 48 MHz oscillator, and if the card requests 50 MHz, it=20
could switch to one of the PLLs. That works as long as the PLLs don't=20
change rate, but if one is configured as driving the CPU clock, it=20
becomes messy.
The thing is, the clocks driver has no way to know whether or not it is=20
"safe" to use a designated parent.

For that reason, in practice, I never actually want to have a clock=20
re-parented - it's almost always a bad idea vs. sticking to the parent=20
clock configured in the DTS.


> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
>  drivers/clk/ingenic/cgu.c | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> index 1f7ba30f5a1b..0c9c8344ad11 100644
> --- a/drivers/clk/ingenic/cgu.c
> +++ b/drivers/clk/ingenic/cgu.c
> @@ -491,22 +491,23 @@ ingenic_clk_calc_div(struct clk_hw *hw,
>  	return div;
>  }
>=20
> -static long
> -ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
> -		       unsigned long *parent_rate)
> +static int ingenic_clk_determine_rate(struct clk_hw *hw,
> +				      struct clk_rate_request *req)
>  {
>  	struct ingenic_clk *ingenic_clk =3D to_ingenic_clk(hw);
>  	const struct ingenic_cgu_clk_info *clk_info =3D=20
> to_clk_info(ingenic_clk);
>  	unsigned int div =3D 1;
>=20
>  	if (clk_info->type & CGU_CLK_DIV)
> -		div =3D ingenic_clk_calc_div(hw, clk_info, *parent_rate, req_rate);
> +		div =3D ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate,
> +					   req->rate);

Sorry but I'm not sure that this works.

You replace the "parent_rate" with the "best_parent_rate", and that=20
means you only check the requested rate vs. the parent with the highest=20
frequency, and not vs. the actual parent that will be used.

Cheers,
-Paul

>  	else if (clk_info->type & CGU_CLK_FIXDIV)
>  		div =3D clk_info->fixdiv.div;
>  	else if (clk_hw_can_set_rate_parent(hw))
> -		*parent_rate =3D req_rate;
> +		req->best_parent_rate =3D req->rate;
>=20
> -	return DIV_ROUND_UP(*parent_rate, div);
> +	req->rate =3D DIV_ROUND_UP(req->best_parent_rate, div);
> +	return 0;
>  }
>=20
>  static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
> @@ -626,7 +627,7 @@ static const struct clk_ops ingenic_clk_ops =3D {
>  	.set_parent =3D ingenic_clk_set_parent,
>=20
>  	.recalc_rate =3D ingenic_clk_recalc_rate,
> -	.round_rate =3D ingenic_clk_round_rate,
> +	.determine_rate =3D ingenic_clk_determine_rate,
>  	.set_rate =3D ingenic_clk_set_rate,
>=20
>  	.enable =3D ingenic_clk_enable,
>=20
> --
> b4 0.11.0-dev-99e3a