Received: by 2002:a05:6358:16cd:b0:dc:6189:e246 with SMTP id r13csp1556912rwl; Fri, 4 Nov 2022 15:53:29 -0700 (PDT) X-Google-Smtp-Source: AMsMyM46Rtp+ugnwM/Gm1zOlugypV/nUG7QTmCki6oEKxRuDCFVsIbNom/Yvb1P5SkXKjfymyT5q X-Received: by 2002:a17:903:22c7:b0:187:190d:da89 with SMTP id y7-20020a17090322c700b00187190dda89mr31649923plg.68.1667602409393; Fri, 04 Nov 2022 15:53:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667602409; cv=none; d=google.com; s=arc-20160816; b=EDGv7rIea8/Ip2f8IGbdTKKXtiqjWWISc87+xPzUfssi9E2jQX/UcPBHSe5ZBFxiL5 IaUtp2PpGD86PDcZR2gkYP65gpTJPwfqt1kVo5FvrmHihaJkXs8EnmlfHgkCtt3vnrtB XuMJgbhflAHhFdtjaW1jy1SbUzMJeWikwrsaRGZanb7UG+ZCWDyO3V3AfC2GJ+3WLwjO kGF6ua+f96rqxgizY20dfSeKoviljkzwmLpt++C90ENhjP9LOvpzDkkmR5550LOL4W2B z9inZhjcz/qenrvXzqNg5XXK7wl0dxmMuru+85RrKOWDJb9nCdv+KAtL8HvFzZ7jkfl1 HYEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=qrAb9WBcxZa2Ls4drWG5rzJJsVV/R9zzooExIZoY3XI=; b=uoqnsuwH6vE/xW6UUQsgSry3e8Sf+f36++wy85uH6h7aX26kIijjqPX4pswc6F2aLf c9QAGaV7Fxcj/Vsm4Pp9KFgmsJEYoYByrQ4ivpHvTzjFOjXUk4Nco3v8E8Si5iXzffrZ WPIZS3z+KXzuz5xgIkG0aD3Rb8nWK7LIzScdOInMFRF7HkZ9LcAyBl+/vFwVrX0taDVG ZH9SIoHgHVSv/kavUn5HKskIsalFjpvIGIOU5L2xJkAqqSjt4s15/J6keR+45SF38+BK zYZBqUMKLS6QT7suHtGWH/Six20CRgBw2MAc3/tlCrBU5xBdrmh8STXjJQ13W6fvU/vE mEJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Akbq8CuO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id i16-20020a170902c95000b0016dc27fb9fbsi1193643pla.117.2022.11.04.15.53.16; Fri, 04 Nov 2022 15:53:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Akbq8CuO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230342AbiKDWpf (ORCPT + 97 others); Fri, 4 Nov 2022 18:45:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230353AbiKDWow (ORCPT ); Fri, 4 Nov 2022 18:44:52 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73C5D69DF4; Fri, 4 Nov 2022 15:40:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667601648; x=1699137648; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zjdmX1zB3aTbVFcJICXaDZe79u/RmhU8f5GNP/klTjA=; b=Akbq8CuOp8BYDkiuXEMTXwQDNmJ5RsIHOaAQkBdvZrULVEBgnqTlGh8o 33ORdXce+qNdS0ehtXrOVq7uNWX2UKX4jiCAjrKasy4ekhuvpeffpqHIu NZSWFgyZ0srE2u2ypN/XvbSZeznN9pITrjdPWQ+nvrqCdDWKql7yqSju+ 4pli0VavKq8wLS70AqTGQ8zR1RyzhV5vDQWJjRgnongPO3IVQkGjYSHy7 85eaaG27fS0vJ1sWV35Rk4QHKpT9IlxPqYtEsOK8o2r5ECfjfQBYvmjG1 3JdrRpCgHGEWUaIx5KilOtc0GLtBhDCsLy070FTKfaHBJWVK33Z9dIDjF Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10521"; a="311840620" X-IronPort-AV: E=Sophos;i="5.96,138,1665471600"; d="scan'208";a="311840620" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2022 15:39:53 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10521"; a="668514159" X-IronPort-AV: E=Sophos;i="5.96,138,1665471600"; d="scan'208";a="668514159" Received: from adhjerms-mobl1.amr.corp.intel.com (HELO rpedgeco-desk.amr.corp.intel.com) ([10.212.227.68]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Nov 2022 15:39:52 -0700 From: Rick Edgecombe To: x86@kernel.org, "H . Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Borislav Petkov , Cyrill Gorcunov , Dave Hansen , Eugene Syromiatnikov , Florian Weimer , "H . J . Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , Randy Dunlap , "Ravi V . Shankar" , Weijiang Yang , "Kirill A . Shutemov" , John Allen , kcc@google.com, eranian@google.com, rppt@kernel.org, jamorris@linux.microsoft.com, dethoma@microsoft.com, akpm@linux-foundation.org Cc: rick.p.edgecombe@intel.com Subject: [PATCH v3 34/37] x86/fpu: Add helper for initing features Date: Fri, 4 Nov 2022 15:36:01 -0700 Message-Id: <20221104223604.29615-35-rick.p.edgecombe@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221104223604.29615-1-rick.p.edgecombe@intel.com> References: <20221104223604.29615-1-rick.p.edgecombe@intel.com> X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If an xfeature is saved in a buffer, the xfeature's bit will be set in xsave->header.xfeatures. The CPU may opt to not save the xfeature if it is in it's init state. In this case the xfeature buffer address cannot be retrieved with get_xsave_addr(). Future patches will need to handle the case of writing to an xfeature that may not be saved. So provide helpers to init an xfeature in an xsave buffer. This could of course be done directly by reaching into the xsave buffer, however this would not be robust against future changes to optimize the xsave buffer by compacting it. In that case the xsave buffer would need to be re-arranged as well. So the logic properly belongs encapsulated in a helper where the logic can be unified. Tested-by: Pengfei Xu Tested-by: John Allen Signed-off-by: Rick Edgecombe --- v2: - New patch arch/x86/kernel/fpu/xstate.c | 58 +++++++++++++++++++++++++++++------- arch/x86/kernel/fpu/xstate.h | 6 ++++ 2 files changed, 53 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 959d4dd64434..665737559a1f 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -934,6 +934,24 @@ static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr) return (void *)xsave + xfeature_get_offset(xcomp_bv, xfeature_nr); } +static int xsave_buffer_access_checks(int xfeature_nr) +{ + /* + * Do we even *have* xsave state? + */ + if (!boot_cpu_has(X86_FEATURE_XSAVE)) + return 1; + + /* + * We should not ever be requesting features that we + * have not enabled. + */ + if (WARN_ON_ONCE(!xfeature_enabled(xfeature_nr))) + return 1; + + return 0; +} + /* * Given the xsave area and a state inside, this function returns the * address of the state. @@ -954,17 +972,7 @@ static void *__raw_xsave_addr(struct xregs_state *xsave, int xfeature_nr) */ void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr) { - /* - * Do we even *have* xsave state? - */ - if (!boot_cpu_has(X86_FEATURE_XSAVE)) - return NULL; - - /* - * We should not ever be requesting features that we - * have not enabled. - */ - if (WARN_ON_ONCE(!xfeature_enabled(xfeature_nr))) + if (xsave_buffer_access_checks(xfeature_nr)) return NULL; /* @@ -984,6 +992,34 @@ void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr) return __raw_xsave_addr(xsave, xfeature_nr); } +/* + * Given the xsave area and a state inside, this function + * initializes an xfeature in the buffer. + * + * get_xsave_addr() will return NULL if the feature bit is + * not present in the header. This function will make it so + * the xfeature buffer address is ready to be retrieved by + * get_xsave_addr(). + * + * Inputs: + * xstate: the thread's storage area for all FPU data + * xfeature_nr: state which is defined in xsave.h (e.g. XFEATURE_FP, + * XFEATURE_SSE, etc...) + * Output: + * 1 if the feature cannot be inited, 0 on success + */ +int init_xfeature(struct xregs_state *xsave, int xfeature_nr) +{ + if (xsave_buffer_access_checks(xfeature_nr)) + return 1; + + /* + * Mark the feature inited. + */ + xsave->header.xfeatures |= BIT_ULL(xfeature_nr); + return 0; +} + #ifdef CONFIG_ARCH_HAS_PKEYS /* diff --git a/arch/x86/kernel/fpu/xstate.h b/arch/x86/kernel/fpu/xstate.h index 5ad47031383b..fb8aae678e9f 100644 --- a/arch/x86/kernel/fpu/xstate.h +++ b/arch/x86/kernel/fpu/xstate.h @@ -54,6 +54,12 @@ extern void fpu__init_cpu_xstate(void); extern void fpu__init_system_xstate(unsigned int legacy_size); extern void *get_xsave_addr(struct xregs_state *xsave, int xfeature_nr); +extern int init_xfeature(struct xregs_state *xsave, int xfeature_nr); + +static inline int xfeature_saved(struct xregs_state *xsave, int xfeature_nr) +{ + return xsave->header.xfeatures & BIT_ULL(xfeature_nr); +} static inline u64 xfeatures_mask_supervisor(void) { -- 2.17.1