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Date:   Sat, 05 Nov 2022 10:33:54 +0000
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v2 56/65] clk: ingenic: cgu: Switch to determine_rate
To:     Maxime Ripard <maxime@cerno.tech>
Cc:     Stephen Boyd <sboyd@kernel.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
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References: <20221018-clk-range-checks-fixes-v2-0-f6736dec138e@cerno.tech>
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Hi Maxime,

Le ven. 4 nov. 2022 =E0 15:59:46 +0100, Maxime Ripard=20
<maxime@cerno.tech> a =E9crit :
> Hi Paul,
>=20
> On Fri, Nov 04, 2022 at 02:31:20PM +0000, Paul Cercueil wrote:
>>  Le ven. 4 nov. 2022 =E0 14:18:13 +0100, Maxime Ripard=20
>> <maxime@cerno.tech> a
>>  =E9crit :
>>  > The Ingenic CGU clocks implements a mux with a set_parent hook,=20
>> but
>>  > doesn't provide a determine_rate implementation.
>>  >
>>  > This is a bit odd, since set_parent() is there to, as its name=20
>> implies,
>>  > change the parent of a clock. However, the most likely candidate=20
>> to
>>  > trigger that parent change is a call to clk_set_rate(), with
>>  > determine_rate() figuring out which parent is the best suited for=20
>> a
>>  > given rate.
>>  >
>>  > The other trigger would be a call to clk_set_parent(), but it's=20
>> far less
>>  > used, and it doesn't look like there's any obvious user for that=20
>> clock.
>>  >
>>  > So, the set_parent hook is effectively unused, possibly because=20
>> of an
>>  > oversight. However, it could also be an explicit decision by the
>>  > original author to avoid any reparenting but through an explicit=20
>> call to
>>  > clk_set_parent().
>>  >
>>  > The driver does implement round_rate() though, which means that=20
>> we can
>>  > change the rate of the clock, but we will never get to change the
>>  > parent.
>>  >
>>  > However, It's hard to tell whether it's been done on purpose or=20
>> not.
>>  >
>>  > Since we'll start mandating a determine_rate() implementation,=20
>> let's
>>  > convert the round_rate() implementation to a determine_rate(),=20
>> which
>>  > will also make the current behavior explicit. And if it was an
>>  > oversight, the clock behaviour can be adjusted later on.
>>=20
>>  So it's partly on purpose, partly because I didn't know about
>>  .determine_rate.
>>=20
>>  There's nothing odd about having a lonely .set_parent callback; in=20
>> my case
>>  the clocks are parented from the device tree.
>>=20
>>  Having the clocks driver trigger a parent change when requesting a=20
>> rate
>>  change sounds very dangerous, IMHO. My MMC controller can be=20
>> parented to the
>>  external 48 MHz oscillator, and if the card requests 50 MHz, it=20
>> could switch
>>  to one of the PLLs. That works as long as the PLLs don't change=20
>> rate, but if
>>  one is configured as driving the CPU clock, it becomes messy.
>>  The thing is, the clocks driver has no way to know whether or not=20
>> it is
>>  "safe" to use a designated parent.
>>=20
>>  For that reason, in practice, I never actually want to have a clock
>>  re-parented - it's almost always a bad idea vs. sticking to the=20
>> parent clock
>>  configured in the DTS.
>=20
> Yeah, and this is totally fine. But we need to be explicit about it.=20
> The
> determine_rate implementation I did in all the patches is an exact
> equivalent to the round_rate one if there was one. We will never ask=20
> to
> change the parent.
>=20
> Given what you just said, I would suggest to set the
> CLK_SET_RATE_NO_REPARENT flag as well.

But that would introduce policy into the driver... The fact that I=20
don't want the MMC parented to the PLLs, doesn't mean that it's an=20
invalid configuration per se.

Cheers,
-Paul

>>=20
>>  > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
>>  > ---
>>  >  drivers/clk/ingenic/cgu.c | 15 ++++++++-------
>>  >  1 file changed, 8 insertions(+), 7 deletions(-)
>>  >
>>  > diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
>>  > index 1f7ba30f5a1b..0c9c8344ad11 100644
>>  > --- a/drivers/clk/ingenic/cgu.c
>>  > +++ b/drivers/clk/ingenic/cgu.c
>>  > @@ -491,22 +491,23 @@ ingenic_clk_calc_div(struct clk_hw *hw,
>>  >  	return div;
>>  >  }
>>  >
>>  > -static long
>>  > -ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
>>  > -		       unsigned long *parent_rate)
>>  > +static int ingenic_clk_determine_rate(struct clk_hw *hw,
>>  > +				      struct clk_rate_request *req)
>>  >  {
>>  >  	struct ingenic_clk *ingenic_clk =3D to_ingenic_clk(hw);
>>  >  	const struct ingenic_cgu_clk_info *clk_info =3D
>>  > to_clk_info(ingenic_clk);
>>  >  	unsigned int div =3D 1;
>>  >
>>  >  	if (clk_info->type & CGU_CLK_DIV)
>>  > -		div =3D ingenic_clk_calc_div(hw, clk_info, *parent_rate,=20
>> req_rate);
>>  > +		div =3D ingenic_clk_calc_div(hw, clk_info, req->best_parent_rate,
>>  > +					   req->rate);
>>=20
>>  Sorry but I'm not sure that this works.
>>=20
>>  You replace the "parent_rate" with the "best_parent_rate", and that=20
>> means
>>  you only check the requested rate vs. the parent with the highest=20
>> frequency,
>>  and not vs. the actual parent that will be used.
>=20
> best_parent_rate is initialized to the current parent rate, not the
> parent with the highest frequency:
> https://elixir.bootlin.com/linux/v6.1-rc3/source/drivers/clk/clk.c#L1471
>=20
> Maxime