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From:   =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
To:     linux-spi@vger.kernel.org, openbmc@lists.ozlabs.org
Cc:     Lee Jones <lee@kernel.org>, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>,
        Mark Brown <broonie@kernel.org>,
        Linus Walleij <linus.walleij@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-gpio@vger.kernel.org
Subject: [PATCH 5/8] ARM: dts: wpcm450: Add FIU SPI controller node
Date:   Sat,  5 Nov 2022 19:59:08 +0100
Message-Id: <20221105185911.1547847-6-j.neuschaefer@gmx.net>
In-Reply-To: <20221105185911.1547847-1-j.neuschaefer@gmx.net>
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Precedence: bulk

Add the SPI controller (FIU, Flash Interface Unit) to the WPCM450
devicetree, according to the newly defined binding, as well as the SHM
(shared memory interface) syscon.

Signed-off-by: Jonathan Neusch=C3=A4fer <j.neuschaefer@gmx.net>
=2D--

This patch depends on the series:

	[PATCH v5 0/6] Nuvoton WPCM450 clock and reset driver
=2D--
 arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nu=
voton-wpcm450.dtsi
index 439f9047ad651..299fcbba3089b 100644
=2D-- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
+++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@ -470,5 +470,21 @@ hg7_pins: mux-hg7 {
 				function =3D "hg7";
 			};
 		};
+
+		fiu: spi-controller@c8000000 {
+			compatible =3D "nuvoton,wpcm450-fiu";
+			#address-cells =3D <1>;
+			#size-cells =3D <0>;
+			reg =3D <0xc8000000 0x1000>, <0xc0000000 0x4000000>;
+			reg-names =3D "control", "memory";
+			clocks =3D <&clk WPCM450_CLK_FIU>;
+			status =3D "disabled";
+		};
+
+		shm: syscon@c8001000 {
+			compatible =3D "nuvoton,wpcm450-shm", "syscon";
+			reg =3D <0xc8001000 0x1000>;
+			reg-io-width =3D <1>;
+		};
 	};
 };
=2D-
2.35.1