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[2620:137:e000::1:20]) by mx.google.com with ESMTP id dd16-20020a1709069b9000b0073d8e26e78bsi559382ejc.960.2022.11.07.01.38.10; Mon, 07 Nov 2022 01:38:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231347AbiKGJVW (ORCPT + 96 others); Mon, 7 Nov 2022 04:21:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229638AbiKGJVU (ORCPT ); Mon, 7 Nov 2022 04:21:20 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 6D1E3F5AF; Mon, 7 Nov 2022 01:21:17 -0800 (PST) Received: from loongson.cn (unknown [10.20.42.77]) by gateway (Coremail) with SMTP id _____8Bx37cMzmhj2_8EAA--.11645S3; Mon, 07 Nov 2022 17:21:16 +0800 (CST) Received: from [10.20.42.77] (unknown [10.20.42.77]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxLeALzmhjs2IOAA--.39954S3; Mon, 07 Nov 2022 17:21:15 +0800 (CST) Subject: Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller To: Krzysztof Kozlowski , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui Cc: Jianmin Lv , Yinbo Zhu , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221107023404.26730-1-liupeibao@loongson.cn> <20221107023404.26730-2-liupeibao@loongson.cn> From: Liu Peibao Message-ID: <196e80d8-f4fb-7393-81a5-bca757c805f5@loongson.cn> Date: Mon, 7 Nov 2022 17:21:15 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit X-CM-TRANSID: AQAAf8DxLeALzmhjs2IOAA--.39954S3 X-CM-SenderInfo: xolx1vpled0qxorr0wxvrqhubq/1tbiAQADCmNno+QOXQABsZ X-Coremail-Antispam: 1Uk129KBjvJXoW7try5GF1fKFyktFyDCF18AFb_yoW8Kw1fpF y7CanxuF40qF43Cws2g3WF9rnxZrn3Jr1S9anxt3yxC34ag343XFW2vF95uFWrGryxXr4U Zr1093W0qFnrJFJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU baAYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44I27wAqx4xG64xvF2 IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4U McvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCYjI0SjxkI62AI1cAE67vIY487Mx kF7I0En4kS14v26r126r1DMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4U MI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67 AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0 cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z2 80aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI 43ZEXa7IU8JfQtUUUUU== X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NICE_REPLY_A, SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/7/22 4:28 PM, Krzysztof Kozlowski wrote: > On 07/11/2022 03:34, Liu Peibao wrote: > > Add commit msg explaining what you are doing here (e.g. the hardware). > I just add this yaml for what I did in patch 1/2 and the header seems enough to describe what I want to, so I did not add the commit log. >> Signed-off-by: Liu Peibao >> --- >> .../loongarch,cpu-interrupt-controller.yaml | 42 +++++++++++++++++++ >> 1 file changed, 42 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> new file mode 100644 >> index 000000000000..30b742661a3f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml >> @@ -0,0 +1,42 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: LoongArch CPU Interrupt Controller >> + >> +description: > >> + On LoongArch the loongarch_cpu_irq_of_init() helper can be used to initialize >> + the 14 CPU IRQs from a devicetree file and create a irq_domain for this IRQ >> + controller. >> + >> + With the irq_domain in place we can describe how the 14 IRQs are wired to the >> + platforms internal interrupt controller cascade. > > This should be the description of hardware, not Linux drivers. > OK, I will remove this in the next version of this patch. >> + >> +maintainers: >> + - Liu Peibao >> + >> +properties: >> + compatible: >> + const: loongarch,cpu-interrupt-controller > > You have exactly one and only one type of CPU interrupt controller for > all your Loongarch designs? All current and all future? All? > It is sure of that "all current and recent designs". It is really hard to limit the design in the distant future. And if there is updating, maybe I will add additional things like this: "loongarch,cpu-interrupt-controller-2.0". BR, Peibao