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From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     Prabhakar <prabhakar.csengg@gmail.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Magnus Damm <magnus.damm@gmail.com>,
        Linus Walleij <linus.walleij@linaro.org>
CC:     "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the GPIO
 pins as interrupts
Thread-Topic: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the
 GPIO pins as interrupts
Thread-Index: AQHY8tHTw1YXCrAdj0KX+iZlhq0xQa40m+uw
Date:   Tue, 8 Nov 2022 07:14:14 +0000
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Hi Prabhakar,


> Subject: [PATCH RFC 2/5] pinctrl: renesas: rzg2l: Fix configuring the GPI=
O
> pins as interrupts
>=20
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>=20
> On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and als=
o
> the pin configs are completely different. This patch makes sure we use th=
e
> appropriate pin configs for each SoC (which is passed as part of the OF
> data) while configuring the GPIO pin as interrupts instead of using
> rzg2l_gpio_configs[] for all the SoCs.
>=20

Looks like you are missing fixes tag.
Fixes: db2e5f21a48ed ("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to h=
andle GPIO interrupt")

As we have already pinctrl support for RZ/G2UL [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/comm=
it/drivers/pinctrl/renesas/pinctrl-rzg2l.c?h=3Dv6.1-rc4&id=3Dbfc69bdbaad141=
ac408e6de86b7e0d771c8e3ccb

Cheers,
Biju

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)
>=20
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index a43824fd9505..dcc495baa678 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -127,6 +127,7 @@ struct rzg2l_dedicated_configs {  struct
> rzg2l_pinctrl_data {
>  	const char * const *port_pins;
>  	const u32 *port_pin_configs;
> +	unsigned int n_port_pin_configs;
>  	struct rzg2l_dedicated_configs *dedicated_pins;
>  	unsigned int n_port_pins;
>  	unsigned int n_dedicated_pins;
> @@ -1122,7 +1123,7 @@ static struct {
>  	}
>  };
>=20
> -static int rzg2l_gpio_get_gpioint(unsigned int virq)
> +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct
> +rzg2l_pinctrl_data *data)
>  {
>  	unsigned int gpioint;
>  	unsigned int i;
> @@ -1131,13 +1132,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int vi=
rq)
>  	port =3D virq / 8;
>  	bit =3D virq % 8;
>=20
> -	if (port >=3D ARRAY_SIZE(rzg2l_gpio_configs) ||
> -	    bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
> +	if (port >=3D data->n_port_pin_configs ||
> +	    bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
>  		return -EINVAL;
>=20
>  	gpioint =3D bit;
>  	for (i =3D 0; i < port; i++)
> -		gpioint +=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]);
> +		gpioint +=3D RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
>=20
>  	return gpioint;
>  }
> @@ -1237,7 +1238,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct
> gpio_chip *gc,
>  	unsigned long flags;
>  	int gpioint, irq;
>=20
> -	gpioint =3D rzg2l_gpio_get_gpioint(child);
> +	gpioint =3D rzg2l_gpio_get_gpioint(child, pctrl->data);
>  	if (gpioint < 0)
>  		return gpioint;
>=20
> @@ -1311,8 +1312,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_c=
hip
> *gc,
>  		port =3D offset / 8;
>  		bit =3D offset % 8;
>=20
> -		if (port >=3D ARRAY_SIZE(rzg2l_gpio_configs) ||
> -		    bit >=3D RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port]))
> +		if (port >=3D pctrl->data->n_port_pin_configs ||
> +		    bit >=3D
> +RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
>  			clear_bit(offset, valid_mask);
>  	}
>  }
> @@ -1517,6 +1518,7 @@ static int rzg2l_pinctrl_probe(struct platform_devi=
ce
> *pdev)  static struct rzg2l_pinctrl_data r9a07g043_data =3D {
>  	.port_pins =3D rzg2l_gpio_names,
>  	.port_pin_configs =3D r9a07g043_gpio_configs,
> +	.n_port_pin_configs =3D ARRAY_SIZE(r9a07g043_gpio_configs),
>  	.dedicated_pins =3D rzg2l_dedicated_pins.common,
>  	.n_port_pins =3D ARRAY_SIZE(r9a07g043_gpio_configs) *
> RZG2L_PINS_PER_PORT,
>  	.n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common),
> @@ -1525,6 +1527,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D=
 {
> static struct rzg2l_pinctrl_data r9a07g044_data =3D {
>  	.port_pins =3D rzg2l_gpio_names,
>  	.port_pin_configs =3D rzg2l_gpio_configs,
> +	.n_port_pin_configs =3D ARRAY_SIZE(rzg2l_gpio_configs),
>  	.dedicated_pins =3D rzg2l_dedicated_pins.common,
>  	.n_port_pins =3D ARRAY_SIZE(rzg2l_gpio_names),
>  	.n_dedicated_pins =3D ARRAY_SIZE(rzg2l_dedicated_pins.common) +
> --
> 2.25.1