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[209.85.219.171]) by smtp.gmail.com with ESMTPSA id 6-20020ac84e86000000b0039cb5c9dbacsm8482151qtp.22.2022.11.08.07.44.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Nov 2022 07:44:32 -0800 (PST) Received: by mail-yb1-f171.google.com with SMTP id 7so13272084ybp.13; Tue, 08 Nov 2022 07:44:31 -0800 (PST) X-Received: by 2002:a25:4fc2:0:b0:6be:afb4:d392 with SMTP id d185-20020a254fc2000000b006beafb4d392mr51553746ybb.604.1667922271344; Tue, 08 Nov 2022 07:44:31 -0800 (PST) MIME-Version: 1.0 References: <20221028165921.94487-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221028165921.94487-6-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 8 Nov 2022 16:44:19 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK To: Prabhakar Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Conor Dooley , Guo Ren , Anup Patel , Atish Patra , Heinrich Schuchardt , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 28, 2022 at 6:59 PM Prabhakar wrote: > From: Lad Prabhakar > > Enable the minimal blocks required for booting the Renesas RZ/Five > SMARC EVK with initramfs. > > Below are the blocks which are enabled: > - CPG > - CPU0 > - DDR (memory regions) > - PINCTRL > - PLIC > - SCIF0 > > As we are reusing the RZ/G2UL SoC base DTSI [0], RZ/G2UL SMARC SoM [1] and > carrier [2] board DTSIs which enables almost all the blocks supported > by the RZ/G2UL SMARC EVK and whereas on RZ/Five SoC we will be gradually > enabling the blocks hence the aliases for ETH/I2C are deleted and rest > of the IP blocks are marked as disabled/deleted. > > [0] arch/arm64/boot/dts/renesas/r9a07g043.dtsi > [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > [2] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi > > Signed-off-by: Lad Prabhakar > --- > v4 -> v5 > * Reworked completely (sort of new patch) Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds