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Date:   Tue, 8 Nov 2022 16:08:44 +0000
From:   Sudeep Holla <sudeep.holla@arm.com>
To:     Pierre Gondois <pierre.gondois@arm.com>
Cc:     linux-kernel@vger.kernel.org,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Len Brown <lenb@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Gavin Shan <gshan@redhat.com>,
        Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kw@linux.com>,
        Jani Nikula <jani.nikula@intel.com>,
        Jakub Kicinski <kuba@kernel.org>,
        linux-arm-kernel@lists.infradead.org,
        linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org
Subject: Re: [PATCH 1/5] cacheinfo: Use riscv's init_cache_level() as generic
 OF implem
Message-ID: <20221108160844.iosdfo2bm6srfexp@bogus>
References: <20221108110424.166896-1-pierre.gondois@arm.com>
 <20221108110424.166896-2-pierre.gondois@arm.com>
 <20221108160323.kqotjshjxr67muaf@bogus>
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On Tue, Nov 08, 2022 at 04:03:23PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > Riscv's implementation of init_of_cache_level() is following
> > the Devicetree Specification v0.3 regarding caches, cf.:
> > - s3.7.3 'Internal (L1) Cache Properties'
> > - s3.8 'Multi-level and Shared Cache Nodes'
> > 
> > Allow reusing the implementation by moving it.
> >
> 
> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
> 

Forgot to mention earlier, I prefer to
s/riscv/RISC-V/
s/implem/implementation/

-- 
Regards,
Sudeep