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From:   Geert Uytterhoeven <geert@linux-m68k.org>
Date:   Tue, 8 Nov 2022 17:02:57 +0100
Message-ID: <CAMuHMdXjZGTNM7pUqxwXd08bjuPEFUuUwKFGx01FVCqOGnc6hQ@mail.gmail.com>
Subject: Re: [PATCH v5 0/7] Add support for Renesas RZ/Five SoC
To:     Conor Dooley <conor@kernel.org>
Cc:     "Lad, Prabhakar" <prabhakar.csengg@gmail.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Magnus Damm <magnus.damm@gmail.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Conor Dooley <conor.dooley@microchip.com>,
        Guo Ren <guoren@kernel.org>, Anup Patel <anup@brainfault.org>,
        Atish Patra <atishp@rivosinc.com>,
        Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
        Biju Das <biju.das.jz@bp.renesas.com>,
        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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Hi Conor,

On Mon, Nov 7, 2022 at 7:17 PM Conor Dooley <conor@kernel.org> wrote:
> On Mon, Nov 07, 2022 at 06:03:41PM +0000, Lad, Prabhakar wrote:
> > On Sun, Oct 30, 2022 at 11:01 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Sun, Oct 30, 2022 at 10:46 PM Conor Dooley <conor@kernel.org> wrote:
> > > > On Sun, Oct 30, 2022 at 10:37:01PM +0000, Lad, Prabhakar wrote:
> > > > > On Sun, Oct 30, 2022 at 6:24 PM Conor Dooley <conor@kernel.org> wrote:
> > > > > > On Fri, Oct 28, 2022 at 05:59:14PM +0100, Prabhakar wrote:
> > > > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > > > > entry-class social infrastructure gateway control and industrial gateway
> > > > > > > control.
> > > > > > >
> > > > > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > > > > (R9A07G043) SoC. Below is the list of IP blocks enabled in the initial
> > > > > > > board DTS which can be used to boot via initramfs on RZ/Five SMARC EVK:
> > > > > > > - AX45MP CPU
> > > > > > > - CPG
> > > > > > > - PINCTRL
> > > > > >
> > > > > > Hey,
> > > > > > Looks like you've got a pair of warnings here from dtbs_check. I tested
> > > > > > this on top of 20221028's next, with the three branches below merged in,
> > > > > > hopefully my merges aren't the source of them:
> > > > > >
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: 'interrupt-controller' is a required property
> > > > > >         From schema: Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > > linux/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: pinctrl@11030000: '#interrupt-cells' is a required property
> > > > > >         From schema: linux/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
> > > > > >
> > > > > Thanks for the review and test. The warnings above are coming from [0]
> > > > > as support for IRQC is missing, once that is added the warnings should
> > > > > go away.
> > > >
> > > > Right. I merged in the stuff in Geert's trees & I don't think I saw any
> > > > pending patches in the cover that I missed. Is there something else that
> > > > adds the support that's not going to make v6.2? I got rid of all the
> > > > dtbs_check warnings for v6.1 and I'd really like to keep things that
> > > > way!
> > > >
> > > Sorry that pacth wasn't posted yet so I hadn't mentioned it in the
> > > cover letter. I'll make sure I get it posted asap and merged for v6.2.

> > BTW on the riscv patchwork I see status as fail "Patch does not apply
> > to for-next" does that mean I need to resend re-basing on your tree?
>
> Nah, I though that Geert would be applying this patchset, no?
> If that's the case, it only needs to apply to his tree.
>
> Geert, are you waiting for an ack from Palmer?

I can take:
  - [PATCH v5 4/7] riscv: dts: renesas: Add initial devicetree for
Renesas RZ/Five SoC
  - [PATCH v5 5/7] riscv: dts: renesas: Add minimal DTS for Renesas
RZ/Five SMARC EVK
  - [PATCH v5 6/7] MAINTAINERS: Add entry for Renesas RISC-V
(4/7 and 5/7 depend on my renesas-arm-dt-for-v6.2 branch) and funnel
them to the SoC-people.

I can take
  - [PATCH v5 3/7] riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
  - [PATCH v5 7/7] riscv: configs: defconfig: Enable Renesas RZ/Five SoC
with an ack from Palmer.

The rest
  - [PATCH v5 1/7] dt-bindings: riscv: Sort the CPU core list alphabetically
  - [PATCH v5 2/7] dt-bindings: riscv: Add Andes AX45MP core to the list
should probably go through the riscv tree, to avoid merge conflicts
when support for other SoCs is added?

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds