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Message-ID: <aa8f5b80-b94e-b685-ed65-8b9c8f453832@redhat.com>
Date:   Tue, 8 Nov 2022 19:16:00 +0100
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Subject: Re: [PATCH 0/3] Check enumeration before MSR save/restore
To:     Pawan Gupta <pawan.kumar.gupta@linux.intel.com>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
        Dave Hansen <dave.hansen@linux.intel.com>, x86@kernel.org,
        "H. Peter Anvin" <hpa@zytor.com>,
        "Rafael J. Wysocki" <rafael@kernel.org>,
        Pavel Machek <pavel@ucw.cz>,
        Andrew Cooper <Andrew.Cooper3@citrix.com>, degoede@redhat.com
Cc:     linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
        Daniel Sneddon <daniel.sneddon@linux.intel.com>,
        antonio.gomez.iglesias@linux.intel.com
References: <cover.1663025154.git.pawan.kumar.gupta@linux.intel.com>
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From:   Hans de Goede <hdegoede@redhat.com>
In-Reply-To: <cover.1663025154.git.pawan.kumar.gupta@linux.intel.com>
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Hi All,

On 9/13/22 01:38, Pawan Gupta wrote:
> Hi,
> 
> This patchset is to fix the "unchecked MSR access error" [1] during S3
> resume. Patch 1/3 adds a feature bit for MSR_IA32_TSX_CTRL.
> 
> Patch 2/3 adds a feature bit for MSR_AMD64_LS_CFG.
> 
> Patch 3/3 adds check for feature bit before adding any speculation
> control MSR to the list of MSRs to save/restore.
> 
> [1] https://lore.kernel.org/lkml/20220906201743.436091-1-hdegoede@redhat.com/
> 
> Pawan Gupta (3):
>   x86/tsx: Add feature bit for TSX control MSR support
>   x86/cpu/amd: Add feature bit for MSR_AMD64_LS_CFG enumeration
>   x86/pm: Add enumeration check before spec MSRs save/restore setup

What is the status of this series ?

To me this seems like a sensible way to solve the problem which
I reported and other similar problems...

Regards,

Hans