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Date:   Tue, 8 Nov 2022 19:39:25 +0100
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Subject: Re: [PATCH v5 3/3] arm64: dts: mt8195: Add venc node
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To:     Tinghan Shen <tinghan.shen@mediatek.com>,
        Ryder Lee <ryder.lee@mediatek.com>,
        Jianjun Wang <jianjun.wang@mediatek.com>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc:     linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        Project_Global_Chrome_Upstream_Group@mediatek.com,
        Irui Wang <irui.wang@mediatek.com>
References: <20221103025656.8714-1-tinghan.shen@mediatek.com>
 <20221103025656.8714-4-tinghan.shen@mediatek.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20221103025656.8714-4-tinghan.shen@mediatek.com>
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On 03/11/2022 03:56, Tinghan Shen wrote:
> Add venc node for mt8195 SoC.
> 
> Signed-off-by: Irui Wang <irui.wang@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied this patch, for the 2/3 we need PCIe maintainer to take the binding 
change or provide an ACked by.

Regards,
Matthias

> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
>   1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 7d74a5211091..dbfc15174de3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -2109,6 +2109,30 @@
>   			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
>   		};
>   
> +		venc: video-codec@1a020000 {
> +			compatible = "mediatek,mt8195-vcodec-enc";
> +			reg = <0 0x1a020000 0 0x10000>;
> +			iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_REC>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>,
> +				 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>;
> +			interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
> +			mediatek,scp = <&scp>;
> +			clocks = <&vencsys CLK_VENC_VENC>;
> +			clock-names = "venc_sel";
> +			assigned-clocks = <&topckgen CLK_TOP_VENC>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
> +			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> +		};
> +
>   		vencsys_core1: clock-controller@1b000000 {
>   			compatible = "mediatek,mt8195-vencsys_core1";
>   			reg = <0 0x1b000000 0 0x1000>;