Date: Tue, 7 Aug 2007 17:33:35 +0200
From: Andi Kleen <andi@firstfloor.org>
To: Daniel J Blueman <daniel.blueman@gmail.com>
Cc: Andi Kleen <andi@firstfloor.org>,
       =?iso-8859-1?Q?C=E9dric?= Augonnet <cedric.augonnet@gmail.com>,
       Linux Kernel <linux-kernel@vger.kernel.org>
Subject: Re: PAT support for i386 and x86_64
Message-ID: <20070807153335.GA1958@one.firstfloor.org>
References: <6278d2220708070534t7096e579uef2ddbb2c997daa6@mail.gmail.com> <20070807141042.GB952@one.firstfloor.org> <6278d2220708070826h2613dd7dr6e3b8001fba3441a@mail.gmail.com>
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On Tue, Aug 07, 2007 at 04:26:06PM +0100, Daniel J Blueman wrote:
> (Intel IA32 ASDM 3A 10-47) "a WC page must never be aliased to a
> cacheable page because WC writes may not check the processor caches."

Yes that is what we're trying to avoid, but it is far more complicated
than you think.

> This is not talking about corrupting the cache generally, but data
> hitting a PCI target twice by (ie) a broken driver.

This can end up with data corruption, machine checks or 
a broken device. All happened.

> > > barrier will hamper progress we do see, as it has done already for
> > > years.
> >
> > Because it's not simple and nobody has done it properly yet.
> 
> Providing only UC and WC types and documenting aliasing problems is
> what is required here.

At least the direct mapping needs to be changed too and any mapping
comming from other sources (/sys/bus/pci, /dev/mem etc.) 
Otherwise you get the dangerous illegal aliases.

The chances of a driver getting this right even when documented
are very small.

BTW i had some prototype patches to address some of this,
but they need much more work to handle all this properly.
Just reprogramming the PAT registers is really the smallest issue.
The IA64 port has done some of the work as an example, unfortunately they
use a strange memory mapping scheme that cannot be easily moved
over. iirc Bjorn identified over 10 potential sources of cache aliases
that all needed to be addressed in the end.

-Andi

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