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From:   Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
To:     Serge Semin <Sergey.Semin@baikalelectronics.ru>,
        Rob Herring <robh+dt@kernel.org>,
        Rob Herring <robh@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
        Cai Huoqing <cai.huoqing@linux.dev>,
        Robin Murphy <robin.murphy@arm.com>,
        Jingoo Han <jingoohan1@gmail.com>,
        Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        =?iso-8859-2?Q?Krzysztof_Wilczy=F1ski?= <kw@linux.com>
CC:     Serge Semin <fancer.lancer@gmail.com>,
        Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,
        Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,
        Frank Li <Frank.Li@nxp.com>,
        Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
        caihuoqing <caihuoqing@baidu.com>, Vinod Koul <vkoul@kernel.org>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v6 17/20] PCI: dwc: Introduce generic resources getter
Thread-Topic: [PATCH v6 17/20] PCI: dwc: Introduce generic resources getter
Thread-Index: AQHY8vD0ArOnmyVAxke/JMPI7hs1ua412tJQ
Date:   Wed, 9 Nov 2022 02:17:45 +0000
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References: <20221107204934.32655-1-Sergey.Semin@baikalelectronics.ru>
 <20221107204934.32655-18-Sergey.Semin@baikalelectronics.ru>
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Hi Serge,

> From: Serge Semin, Sent: Tuesday, November 8, 2022 5:50 AM
>=20
> Currently the DW PCIe Root Port and Endpoint CSR spaces are retrieved in
> the separate parts of the DW PCIe core driver. It doesn't really make
> sense since the both controller types have identical set of the core CSR
> regions: DBI, DBI CS2 and iATU/eDMA. Thus we can simplify the DW PCIe Hos=
t
> and EP initialization methods by moving the platform-specific registers
> space getting and mapping into a common method. It gets to be even more
> justified seeing the CSRs base address pointers are preserved in the
> common DW PCIe descriptor. Note all the OF-based common DW PCIe settings
> initialization will be moved to the new method too in order to have a
> single function for all the generic platform properties handling in singl=
e
> place.
>=20
> A nice side-effect of this change is that the pcie-designware-host.c and
> pcie-designware-ep.c drivers are cleaned up from all the direct dw_pcie
> storage modification, which makes the DW PCIe core, Root Port and Endpoin=
t
> modules more coherent.
>=20
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Rob Herring <robh@kernel.org>
>=20
> ---
>=20
> Changelog v3:
> - This is a new patch created on v3 lap of the series.
>=20
> Changelog v4:
> - Convert the method name from dw_pcie_get_res() to
>   dw_pcie_get_resources(). (@Bjorn)
> ---
>  .../pci/controller/dwc/pcie-designware-ep.c   | 26 +------
>  .../pci/controller/dwc/pcie-designware-host.c | 15 +---
>  drivers/pci/controller/dwc/pcie-designware.c  | 75 ++++++++++++++-----
>  drivers/pci/controller/dwc/pcie-designware.h  |  3 +
>  4 files changed, 65 insertions(+), 54 deletions(-)
>=20
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pc=
i/controller/dwc/pcie-designware-ep.c
> index 237bb01d7852..80a64b63c055 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -13,8 +13,6 @@
>  #include <linux/pci-epc.h>
>  #include <linux/pci-epf.h>
>=20
> -#include "../../pci.h"
> -
>  void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
>  {
>  	struct pci_epc *epc =3D ep->epc;
> @@ -688,29 +686,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
>  	struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep);
>  	struct device *dev =3D pci->dev;
>  	struct platform_device *pdev =3D to_platform_device(dev);
> -	struct device_node *np =3D dev->of_node;

Removing this np causes the following build error if CONFIG_PCIE_DW_EP is e=
nabled:
---
  CC      drivers/pci/controller/dwc/pcie-designware-ep.o
drivers/pci/controller/dwc/pcie-designware-ep.c: In function 'dw_pcie_ep_in=
it':
drivers/pci/controller/dwc/pcie-designware-ep.c:751:35: error: 'np' undecla=
red (first use in this function); did you mean 'ep'?
  751 |         ret =3D of_property_read_u8(np, "max-functions", &epc->max_=
functions);
      |                                   ^~
      |                                   ep
drivers/pci/controller/dwc/pcie-designware-ep.c:751:35: note: each undeclar=
ed identifier is reported only once for each function it appears in
---

So, we should keep the np or use "dev->of_node" to the of_property_read_u8(=
).

Best regards,
Yoshihiro Shimoda