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Date:   Wed, 09 Nov 2022 18:20:48 +0000
Message-ID: <86tu38oupr.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     Mukesh Ojha <quic_mojha@quicinc.com>
Cc:     <linux-arm-kernel@lists.infradead.org>, <catalin.marinas@arm.com>,
        <will@kernel.org>, Thomas Gleixner <tglx@linutronix.de>,
        lkml <linux-kernel@vger.kernel.org>
Subject: Re: Query on handling some special Group0 interrupt in Linux
In-Reply-To: <d7b70de6-cd7f-3724-3449-5b838a478277@quicinc.com>
References: <d7b70de6-cd7f-3724-3449-5b838a478277@quicinc.com>
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On Wed, 09 Nov 2022 16:20:35 +0000,
Mukesh Ojha <quic_mojha@quicinc.com> wrote:
> 
> Hi,
> 
> I was working on a use case where both el2/el3 are implemented and we
> have a watchdog interrupt (SPI), which is used for detecting software
> hangs and cause device reset; If that interrupt's current cpu affinity
> is on a core, where interrupts are disabled, we won't be able to serve
> it or if this interrupt comes on a core which has interrupt enabled,
> calling panic() or with smp_send_stop(), we would not be able
> to know the call stack of the other cores which is running with
> interrupt disabled.
> 
> I was thinking of configuring both a watchdog irq(SPI) and IPI_STOP
> (SGI) or any reserve IPI as an FIQ. And from the watchdog irq handler,
> I was thinking of calling panic() which eventually sends IPI_STOP(SGI
> FIQ) to all the cores. And with this we will able to dump all the core
> call stack.
> 
> I am able to achieve this but wanted to know if this is acceptable to
> the community to support/allow such use cases like above and enable
> group0 interrupt from GIC for some special use cases.

For a start, we only deal with Group-1 interrupts in Linux. Group-0
interrupts are for the firmware, and we really don't want to see them
(this is consistent with your HW having EL3). We also mask IRQ and FIQ
at the same time, so this is a non-starter.

If you want to be able to deliver an interrupt while the interrupts
are masked, what you are looking for is the NMI framework, for which
you can register SPIs as (pseudo-)NMI.

This is of course assuming that you're using GICv3. If you're using an
older version of the architecture, we don't have a good solution for
you, unfortunately.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.