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From:   Jan Petrous <jan.petrous@nxp.com>
To:     Chester Lin <clin@suse.com>, Andrew Lunn <andrew@lunn.ch>
CC:     =?iso-8859-1?Q?Andreas_F=E4rber?= <afaerber@suse.de>,
        Rob Herring <robh@kernel.org>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        dl-S32 <S32@nxp.com>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Matthias Brugger <mbrugger@suse.com>
Subject: RE: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC
 dwmac glue driver
Thread-Topic: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC
 dwmac glue driver
Thread-Index: AQHY7tOAA/zZjStEYkyi6JcYkhk32q4r3zqAgAHj5ACAAON+gIAIlgXQ
Date:   Wed, 9 Nov 2022 22:55:11 +0000
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Hi Chester,
=20
> Hi Andrew and Andreas,
>=20
> On Thu, Nov 03, 2022 at 11:05:30PM +0100, Andrew Lunn wrote:
> > > > > +      - description: Main GMAC clock
> > > > > +      - description: Peripheral registers clock
> > > > > +      - description: Transmit SGMII clock
> > > > > +      - description: Transmit RGMII clock
> > > > > +      - description: Transmit RMII clock
> > > > > +      - description: Transmit MII clock
> > > > > +      - description: Receive SGMII clock
> > > > > +      - description: Receive RGMII clock
> > > > > +      - description: Receive RMII clock
> > > > > +      - description: Receive MII clock
> > > > > +      - description:
> > > > > +          PTP reference clock. This clock is used for programmin=
g the
> > > > > +          Timestamp Addend Register. If not passed then the syst=
em
> > > > > +          clock will be used.
> >
> > > Not clear to me has been whether the PHY mode can be switched at
> runtime
> > > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed b=
y
> board
> > > design.
> >
> > Does the hardware support 1000BaseX? Often the hardware implementing
> > SGMII can also do 1000BaseX, since SGMII is an extended/hacked up
> > 1000BaseX.
> >
> > If you have an SFP connected to the SERDES, a fibre module will want
> > 1000BaseX and a copper module will want SGMII. phylink will tell you
> > what phy-mode you need to use depending on what module is in the
> > socket. This however might be a mute point, since both of these are
> > probably using the SGMII clocks.
> >
> > Of the other MII modes listed, it is very unlikely a runtime swap will
> > occur.
> >
> >       Andrew
>=20
> Here I just focus on GMAC since there are other LAN interfaces that S32
> family
> uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1]
> provided
> on NXP website, theoretically GMAC can run SGMII in 1000Mbps and
> 2500Mbps so I
> assume that supporting 1000BASE-X could be achievable. I'm not sure if an=
y
> S32
> board variant might have SFP ports but RJ-45 [1000BASE-T] should be the
> major
> type used on S32G-EVB and S32G-RDB2.
>=20
> @NXP, please feel free to correct me if anything wrong.
>=20

NXP eval boards (EVB or RDB) have also 2.5G PHYs, so together with SerDes
driver we support 100M/1G/2.5G on such copper PHYs.=20

/Jan

--
NXP Czechia, AP Ethernet