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From:   Jan Petrous <jan.petrous@nxp.com>
To:     Andrew Lunn <andrew@lunn.ch>
CC:     Chester Lin <clin@suse.com>,
        =?iso-8859-1?Q?Andreas_F=E4rber?= <afaerber@suse.de>,
        Rob Herring <robh@kernel.org>,
        "David S. Miller" <davem@davemloft.net>,
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        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
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        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        Matthias Brugger <mbrugger@suse.com>
Subject: RE: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC
 dwmac glue driver
Thread-Topic: [EXT] Re: [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC
 dwmac glue driver
Thread-Index: AQHY7tOAA/zZjStEYkyi6JcYkhk32q4r3zqAgAHj5ACAAON+gIAIlgXQgAAD14CAAJKUkA==
Date:   Thu, 10 Nov 2022 08:51:43 +0000
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Hi Andrew,

> > > Here I just focus on GMAC since there are other LAN interfaces that S=
32
> > > family
> > > uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1=
]
> > > provided
> > > on NXP website, theoretically GMAC can run SGMII in 1000Mbps and
> > > 2500Mbps so I
> > > assume that supporting 1000BASE-X could be achievable. I'm not sure i=
f
> any
> > > S32
> > > board variant might have SFP ports but RJ-45 [1000BASE-T] should be t=
he
> > > major
> > > type used on S32G-EVB and S32G-RDB2.
> > >
> > > @NXP, please feel free to correct me if anything wrong.
> > >
> >
> > NXP eval boards (EVB or RDB) have also 2.5G PHYs, so together with SerD=
es
> > driver we support 100M/1G/2.5G on such copper PHYs.
>=20
> Hi Jan
>=20
> Does the SERDES clock need to change when going between 1000BaseX and
> 2500BaseX?
>=20
> If so, it sounds like Linux not having control of that clock is going
> to limit what can be supported.

No, the SerDes clock remains the same, the change is done internally, witho=
ut
any necessity of clock change intervention by GMAC driver.

/Jan