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Date:   Fri, 11 Nov 2022 12:31:15 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc:     martin.petersen@oracle.com, jejb@linux.ibm.com,
        andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        konrad.dybcio@somainline.org, robh+dt@kernel.org,
        quic_cang@quicinc.com, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-phy@lists.infradead.org, linux-scsi@vger.kernel.org,
        dmitry.baryshkov@linaro.org, ahalaney@redhat.com
Subject: Re: [PATCH v2 02/15] phy: qcom-qmp-ufs: Add support for configuring
 PHY in HS Series B mode
Message-ID: <Y23zO68Bb5R0xLq/@matsya>
References: <20221031180217.32512-1-manivannan.sadhasivam@linaro.org>
 <20221031180217.32512-3-manivannan.sadhasivam@linaro.org>
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In-Reply-To: <20221031180217.32512-3-manivannan.sadhasivam@linaro.org>
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On 31-10-22, 23:32, Manivannan Sadhasivam wrote:
> Add separate tables_hs_b instance to allow the PHY driver to configure the
> PHY in HS Series B mode. The individual SoC configs need to supply the
> serdes register setting in tables_hs_b and the UFS driver can request the
> Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index cdfda4e6d575..4c6a2b5afc9a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -20,6 +20,8 @@
>  #include <linux/reset.h>
>  #include <linux/slab.h>
>  
> +#include <ufs/unipro.h>
> +
>  #include <dt-bindings/phy/phy.h>
>  
>  #include "phy-qcom-qmp.h"
> @@ -549,6 +551,8 @@ struct qmp_phy_cfg {
>  
>  	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
>  	const struct qmp_phy_cfg_tables tables;
> +	/* Additional sequence for HS Series B */
> +	const struct qmp_phy_cfg_tables tables_hs_b;

what am i missing, where was tables_hs_b added?

>  
>  	/* clock ids to be requested */
>  	const char * const *clk_list;
> @@ -582,6 +586,7 @@ struct qmp_phy_cfg {
>   * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
>   * @pcs_misc: iomapped memory space for lane's pcs_misc
>   * @qmp: QMP phy to which this lane belongs
> + * @mode: PHY mode configured by the UFS driver
>   */
>  struct qmp_phy {
>  	struct phy *phy;
> @@ -594,6 +599,7 @@ struct qmp_phy {
>  	void __iomem *rx2;
>  	void __iomem *pcs_misc;
>  	struct qcom_qmp *qmp;
> +	u32 mode;
>  };
>  
>  /**
> @@ -983,6 +989,8 @@ static int qmp_ufs_power_on(struct phy *phy)
>  	int ret;
>  
>  	qmp_ufs_serdes_init(qphy, &cfg->tables);
> +	if (qphy->mode == PHY_MODE_UFS_HS_B)
> +		qmp_ufs_serdes_init(qphy, &cfg->tables_hs_b);
>  
>  	qmp_ufs_lanes_init(qphy, &cfg->tables);
>  
> @@ -1070,6 +1078,15 @@ static int qmp_ufs_disable(struct phy *phy)
>  	return qmp_ufs_exit(phy);
>  }
>  
> +static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> +	struct qmp_phy *qphy = phy_get_drvdata(phy);
> +
> +	qphy->mode = mode;
> +
> +	return 0;
> +}
> +
>  static int qmp_ufs_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
>  {
>  	struct qcom_qmp *qmp = dev_get_drvdata(dev);
> @@ -1105,6 +1122,7 @@ static int qmp_ufs_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
>  static const struct phy_ops qcom_qmp_ufs_ops = {
>  	.power_on	= qmp_ufs_enable,
>  	.power_off	= qmp_ufs_disable,
> +	.set_mode	= qmp_ufs_set_mode,
>  	.owner		= THIS_MODULE,
>  };
>  
> -- 
> 2.25.1

-- 
~Vinod