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Message-ID: <57298a3b-443b-b49b-c395-e2d6420ad20b@quicinc.com>
Date:   Fri, 11 Nov 2022 16:33:06 +0530
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Subject: Re: [PATCH v2 10/10] arm64: dts: qcom: sc8280xp: Add bwmon instances
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To:     Bjorn Andersson <quic_bjorande@quicinc.com>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@somainline.org>,
        "Rob Herring" <robh+dt@kernel.org>
CC:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Georgi Djakov <djakov@kernel.org>,
        Mike Tipton <quic_mdtipton@quicinc.com>,
        Johan Hovold <johan+linaro@kernel.org>,
        <linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20221111032515.3460-1-quic_bjorande@quicinc.com>
 <20221111032515.3460-11-quic_bjorande@quicinc.com>
From:   Sibi Sankar <quic_sibis@quicinc.com>
In-Reply-To: <20221111032515.3460-11-quic_bjorande@quicinc.com>
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On 11/11/22 08:55, Bjorn Andersson wrote:
> Add the two bwmon instances and define votes for CPU -> LLCC and LLCC ->
> DDR, with bandwidth values based on the downstream DeviceTree.
> 
> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Tested-by: Steev Klimaszewski <steev@kali.org>

Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>

> ---
> 
> Changes since v1:
> - Added "cpu" to compatible for the CPU-subsystem bwmon instance
> 
>   arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 91 ++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 2ac8f5204905..62e9dd8a2f07 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1287,6 +1287,97 @@
>   			};
>   		};
>   
> +		pmu@9091000 {
> +			compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
> +			reg = <0 0x9091000 0 0x1000>;
> +
> +			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
> +
> +			operating-points-v2 = <&llcc_bwmon_opp_table>;
> +
> +			llcc_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <762000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <1720000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <2086000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <2597000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <2929000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <3879000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <5161000>;
> +				};
> +				opp-7 {
> +					opp-peak-kBps = <5931000>;
> +				};
> +				opp-8 {
> +					opp-peak-kBps = <6515000>;
> +				};
> +				opp-9 {
> +					opp-peak-kBps = <7980000>;
> +				};
> +				opp-10 {
> +					opp-peak-kBps = <8136000>;
> +				};
> +				opp-11 {
> +					opp-peak-kBps = <10437000>;
> +				};
> +				opp-12 {
> +					opp-peak-kBps = <12191000>;
> +				};
> +			};
> +		};
> +
> +		pmu@90b6400 {
> +			compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
> +			reg = <0 0x090b6400 0 0x600>;
> +
> +			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
> +			operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> +			cpu_bwmon_opp_table: opp-table {
> +				compatible = "operating-points-v2";
> +
> +				opp-0 {
> +					opp-peak-kBps = <2288000>;
> +				};
> +				opp-1 {
> +					opp-peak-kBps = <4577000>;
> +				};
> +				opp-2 {
> +					opp-peak-kBps = <7110000>;
> +				};
> +				opp-3 {
> +					opp-peak-kBps = <9155000>;
> +				};
> +				opp-4 {
> +					opp-peak-kBps = <12298000>;
> +				};
> +				opp-5 {
> +					opp-peak-kBps = <14236000>;
> +				};
> +				opp-6 {
> +					opp-peak-kBps = <15258001>;
> +				};
> +			};
> +		};
> +
>   		system-cache-controller@9200000 {
>   			compatible = "qcom,sc8280xp-llcc";
>   			reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;