Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20221111094238.1640-1-linux.amoon@gmail.com> <20221111094238.1640-3-linux.amoon@gmail.com>
In-Reply-To: <20221111094238.1640-3-linux.amoon@gmail.com>
From:   Peter Geis <pgwipeout@gmail.com>
Date:   Fri, 11 Nov 2022 08:02:31 -0500
Message-ID: <CAMdYzYpi_9B+riQSMk+cjRLd-b_TTi2rQUD7P5PUg_Fd5dGeMA@mail.gmail.com>
Subject: Re: [linux-next-v1 3/3] arm64: dts: rockchip: Fix ethernet reset node
 Rock 3A sbc
To:     Anand Moon <linux.amoon@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Heiko Stuebner <heiko@sntech.de>,
        Chukun Pan <amadeus@jmu.edu.cn>,
        Michael Riesch <michael.riesch@wolfvision.net>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Fri, Nov 11, 2022 at 4:44 AM Anand Moon <linux.amoon@gmail.com> wrote:
>
> Add support for snps,reset-gpio reset ethernet gpio pins and
> drop the mdio reset code.

Nack, the snps,reset-gpio is depreciated in favor of the mdio-reset
code. See [0].

>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
>  .../boot/dts/rockchip/rk3568-rock-3a.dts      | 19 ++++++++-----------
>  1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> index 16fff1ada195..9172cf60b867 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> @@ -258,6 +258,11 @@ &gmac1 {
>         assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
>         assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
>         clock_in_out = "input";
> +       snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
> +       snps,reset-active-low;
> +       /* Reset time is 20ms, 100ms for rtl8211f */
> +       snps,reset-delays-us = <0 20000 100000>;
> +       phy-supply = <&vcc_3v3>;

The phy supply shouldn't be part of this patch.

>         phy-handle = <&rgmii_phy1>;
>         phy-mode = "rgmii";
>         pinctrl-names = "default";
> @@ -267,6 +272,9 @@ &gmac1m1_rx_bus2
>                      &gmac1m1_rgmii_clk
>                      &gmac1m1_clkinout
>                      &gmac1m1_rgmii_bus>;
> +
> +       tx_delay = <0x4f>;
> +       rx_delay = <0x26>;

Delays should move to your rgmii patch. Have you tested these to
ensure they are in the middle of the functional range for this board?

>         status = "okay";
>  };
>
> @@ -583,11 +591,6 @@ &mdio1 {
>         rgmii_phy1: ethernet-phy@0 {
>                 compatible = "ethernet-phy-ieee802.3-c22";
>                 reg = <0x0>;
> -               pinctrl-names = "default";
> -               pinctrl-0 = <&eth_phy_rst>;
> -               reset-assert-us = <20000>;
> -               reset-deassert-us = <100000>;
> -               reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
>         };
>  };
>
> @@ -625,12 +628,6 @@ vcc_mipi_en: vcc_mipi_en {
>                 };
>         };
>
> -       ethernet {
> -               eth_phy_rst: eth_phy_rst {
> -                       rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
> -               };
> -       };
> -
>         hym8563 {
>                 hym8563_int: hym8563-int {
>                         rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
> --
> 2.38.1
>
[0] https://elixir.bootlin.com/linux/v6.1-rc4/source/Documentation/devicetree/bindings/net/snps,dwmac.yaml#L222
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip