Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp3881431rwb; Sat, 12 Nov 2022 15:31:11 -0800 (PST) X-Google-Smtp-Source: AA0mqf5RBQT/doWctn7pm7aXF8iMaKfUdmisA69q52Nfe3pRZs5dzUlr8nOp0ArCWsNMDxAjUUsw X-Received: by 2002:a05:6402:5383:b0:461:f919:caa4 with SMTP id ew3-20020a056402538300b00461f919caa4mr6704625edb.255.1668295870904; Sat, 12 Nov 2022 15:31:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668295870; cv=none; d=google.com; s=arc-20160816; b=lsyWDNzs0sT1MwWHPKhJviBBwu4JJofiIQrMb12pUVFg/KbTNhkmRaLftrLoYn2hEt YgRGQEqkJTSVRx8ZnlgY0gZ6JTzNfNVkm6sQeVBP3kZV5c7ltut9BhqgDo5lcvszasNR Suf8PimhbELJViMyaJvW570XtVbth5bvu9pwdLeiQRCDdFhFcPHVnLAfrxytLxCtMqWK nqu87E7v1PfhM9EtQP2jQ4YM9/8SoR5l9WTu5a4E9zvXC8HU3vN1Or+XcbL+6hn0bZs3 5sxNwaCg1uWjOkz6w/xlT40Q91vepcgFByVCLAwmu/7Za7mh/81GntTDXWZY+KbcV6VN sFGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:subject :from:content-language:references:cc:to:user-agent:mime-version:date :message-id:dkim-signature; bh=ObPzrzs7HkuXWqb/Hm/pvn03m1dpj1pmmiupPueD+24=; b=q+olz7HVkHXgkIpWyGPi8ephpK+/SdknHZQIPO1smbAlUEMj7swBydU9NI5Ga8QBwv gAMjln2zWVGfbBauL+0HSHHc5mBPhor7xhZYtQuV+80Ue8v86THHsjJAgNLSr0AA8tNM GPpGGDeButDNLNeN5HQFbFoPcf3on9XtvrTpAuPwMg/kXv2nMp9h5m1Ug2YtpzeV/RXv ejaFzHNdquAFcixihad6dmEptbjymxqxcrVf9iHiQmU6SVcdbWmihY/kcD18td/nefFa 0tPMllUoOa2QktsQJzKkGMeOBEgRc9S1hsFiy9gUIiRDgcVwCXD3Oj0UmM/bCzGMybQ6 xV7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@digitalocean.com header.s=google header.b=P52pDzOK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=digitalocean.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id m26-20020a50ef1a000000b00461865aae72si5093583eds.219.2022.11.12.15.30.48; Sat, 12 Nov 2022 15:31:10 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@digitalocean.com header.s=google header.b=P52pDzOK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=digitalocean.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234941AbiKLWdu (ORCPT + 90 others); Sat, 12 Nov 2022 17:33:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231814AbiKLWds (ORCPT ); Sat, 12 Nov 2022 17:33:48 -0500 Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F47014D0B for ; Sat, 12 Nov 2022 14:33:47 -0800 (PST) Received: by mail-qv1-xf33.google.com with SMTP id j6so5710354qvn.12 for ; Sat, 12 Nov 2022 14:33:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=digitalocean.com; s=google; h=content-transfer-encoding:in-reply-to:subject:from:content-language :references:cc:to:user-agent:mime-version:date:message-id:from:to:cc :subject:date:message-id:reply-to; bh=ObPzrzs7HkuXWqb/Hm/pvn03m1dpj1pmmiupPueD+24=; b=P52pDzOKLqNpueol/zFYV61tVVAEOij8E4TwX/Rnt0lkrzQwo/quM5rEIXj4ssfKTX zhM1j72PfhBL1z/Y6rNuejwrDLpgllop6c1ydULxJ34GHBn1AOA+kMOhH89AqMDneQrV tm19w50+8zw/SGZ/HlRCQdzTgHDbM4n5E+QHY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:subject:from:content-language :references:cc:to:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ObPzrzs7HkuXWqb/Hm/pvn03m1dpj1pmmiupPueD+24=; b=xMM9BxGlAHN/uzSoLfxf6EZ2w7rJnkh4R4Z14sb5ewGdEgWdBox3CUYDSkysnAsnJ6 MkBwJotxLAvn0a4eEPyjtktMftQHwhoL6g/QptDk3UDOe8z8pW6IWw19c5ruW6GsUHKr 2FBG3iKNblmWtS0kH11nuMWNpIp5R9t3mPxdGD2jGu3mNVSrk1AbPoqL+v0fFBPoGk+b inbAjj08EPyUzRPXGJNhcoA/+NfGdZ4me84lUKZE1gHVF4THRqqa5rUiK1vFg5jK0TvZ A5Vg8LpG6VvZJnRCccyIHzIpdnYLbE8LVTYzQMA9bLyZ6Y8RwRK2xrfJu7IcwHqoeK46 QFCA== X-Gm-Message-State: ANoB5pmmiS109GvCVeHswlbpDlkWr1eDQc8qFdpCNtaDjYH684t6LoN7 T5zIS5xHz3oiib0lmVQoXVwTsg== X-Received: by 2002:a05:6214:428d:b0:4b3:e8bc:b06d with SMTP id og13-20020a056214428d00b004b3e8bcb06dmr7431669qvb.72.1668292426374; Sat, 12 Nov 2022 14:33:46 -0800 (PST) Received: from [192.168.2.110] (107-142-220-210.lightspeed.wlfrct.sbcglobal.net. [107.142.220.210]) by smtp.gmail.com with ESMTPSA id i5-20020a05620a404500b006fb11eee465sm3913431qko.64.2022.11.12.14.33.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 12 Nov 2022 14:33:45 -0800 (PST) Message-ID: Date: Sat, 12 Nov 2022 17:33:44 -0500 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 To: Sandipan Das , Peter Zijlstra Cc: Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , Dave Hansen , Ravi Bangoria , x86@kernel.org, "H. Peter Anvin" , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221027133511.161922-1-lyan@digtalocean.com> Content-Language: en-US From: Liang Yan Subject: Re: [PATCH] arch/x86/events/amd/core.c: Return -ENODEV when CPU does not have PERFCTL_CORE bit In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/31/22 10:28, Sandipan Das wrote: > Hi Liang, Peter, > > On 10/31/2022 6:29 PM, Peter Zijlstra wrote: >> On Thu, Oct 27, 2022 at 09:35:11AM -0400, Liang Yan wrote: >>> After disabling cpu.perfctr_core in qemu, I noticed that the guest kernel >>> still loads the pmu driver while the cpuid does not have perfctl_core. >>> >>> The test is running on an EPYC Rome machine. >>> root@ubuntu-s-4vcpu-8gb-amd-nyc1-01:~# lscpu | grep perfctl >>> root@ubuntu-s-4vcpu-8gb-amd-nyc1-01:~# >>> root@ubuntu-s-4vcpu-8gb-amd-nyc1-01:~# dmesg | grep PMU >>> [ 0.732097] Performance Events: AMD PMU driver. >>> >>> By further looking, >>> >>> ==> init_hw_perf_events >>> ==> amd_pmu_init >>> ==> amd_core_pmu_init >>> ==> >>> if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) >>> return 0; >>> >>> With returning 0, it will bypass amd_pmu_init and return 0 to >>> init_hw_perf_events, and continue the initialization. >>> >>> I am not a perf expert and not sure if it is expected for AMD PMU, >>> otherwise, it would be nice to return -ENODEV instead. >>> >>> New output after the change: >>> root@ubuntu-s-4vcpu-8gb-amd-nyc1-01:~# dmesg | grep PMU >>> [ 0.531609] Performance Events: no PMU driver, software events only. >>> >>> Signed-off-by: Liang Yan >> Looks about right, Ravi? >> >>> --- >>> arch/x86/events/amd/core.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c >>> index 8b70237c33f7..34d3d2944020 100644 >>> --- a/arch/x86/events/amd/core.c >>> +++ b/arch/x86/events/amd/core.c >>> @@ -1335,7 +1335,7 @@ static int __init amd_core_pmu_init(void) >>> int i; >>> >>> if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) >>> - return 0; >>> + return -ENODEV; >>> > There are four legacy counters that are always available even when PERFCTR_CORE > is absent. This is why the code returns 0 here. I found this to be a bit confusing > as well during PerfMonV2 development so I wrote the following patch but forgot to > send it out. Hi Sandipan, Thanks for the classification. Do these legacy counters belong to the AMD PMU property from a VM perspective? I mean, if I want to disable PMU for an AMD vcpu for some reason, is it possible to disable perfctr_core and the four counters, or is this not logical since the four counters could not be disabled from the bare-metal level? I asked because I saw 'pmu' could be disabled for Intel and ARM, but it seems not for AMD. Also, could you please list the four legacy counters here? Thanks, Liang > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > index 262e39a85031..d3eb7b2f4dda 100644 > --- a/arch/x86/events/amd/core.c > +++ b/arch/x86/events/amd/core.c > @@ -1345,6 +1345,14 @@ static int __init amd_core_pmu_init(void) > u64 even_ctr_mask = 0ULL; > int i; > > + /* > + * All processors support four PMCs even when X86_FEATURE_PERFCTR_CORE > + * is unavailable. They are programmable via the PERF_LEGACY_CTLx and > + * PERF_LEGACY_CTRx registers which have the same address as that of > + * MSR_K7_EVNTSELx and MSR_K7_PERFCTRx. For Family 17h+, these are > + * legacy aliases of PERF_CTLx and PERF_CTRx respectively. Hence, not > + * returning -ENODEV here. > + */ > if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) > return 0; > > > If this looks good to you, I will post it. > > - Sandipan >