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References: <20221110150035.2824580-1-adeep@lexina.in> <20221110150035.2824580-5-adeep@lexina.in>
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From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Sun, 13 Nov 2022 00:01:33 +0100
Message-ID: <CAFBinCCch3RsJbnA602tH924umRVdbgr-20g2F3mYLWCDrkg4Q@mail.gmail.com>
Subject: Re: [PATCH 4/4] arm64: dts: docs: Update mmc meson-gx documentation
 for new config option amlogic,mmc-phase
To:     Vyacheslav Bocharov <adeep@lexina.in>
Cc:     linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org
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Hi Vyacheslav,

On Thu, Nov 10, 2022 at 4:01 PM Vyacheslav Bocharov <adeep@lexina.in> wrote:
[...]
> +- amlogic,mmc-phases: 3-element array of clock phases for core, tx, rx clock with values:
> +       0: CLK_PHASE_0 - 0 phase
> +       1: CLK_PHASE_90 - 90 phase
> +       2: CLK_PHASE_180 - 180 phase
> +       3: CLK_PHASE_270 - 270 phase
As mentioned in another patch: I'd go with the human readable values
(0, 90, 180, 270) instead of the register bits.

[...]
> +               amlogic,mmc-phases = <CLK_PHASE_180 CLK_PHASE_0 CLK_PHASE_0>;
Also I *think* the format here is not correct, for an array of three
u32 values this should be:
  amlogic,mmc-phases = <CLK_PHASE_180>, <CLK_PHASE_0>, <CLK_PHASE_0>;


Best regards,
Martin