Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp3974805rwb; Sat, 12 Nov 2022 18:07:44 -0800 (PST) X-Google-Smtp-Source: AA0mqf4VY9AgMov648Od3Yw7ozCBxkIsqBQN8mfW5IsvO1phbfTt+8h3ljptAJ+jN6tTiQRQ6fnZ X-Received: by 2002:a17:907:920d:b0:7aa:97c7:2c05 with SMTP id ka13-20020a170907920d00b007aa97c72c05mr6550073ejb.367.1668305264650; Sat, 12 Nov 2022 18:07:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668305264; cv=none; d=google.com; s=arc-20160816; b=YqKfAdPwgIBJwMJkUJ3p8rxyFh/VvroMnPvmmPDrwW1UL6C58/VryDY6L0dFVQy8nO dA6aKy3GRNhqTRXnWj0+rwYGxah3Ez5eTIm+yndS+TrWR76hDbX2ELeSH/VAA0kOJTLZ 31IXO5OZLKwHLuqCqeoC90e9S9go854lEh7D9/jZP+PsGy00gLXYgyECORRm7KkTJcMb 7QEiEOVFv0Lh/5RKi/CRYl0B9mhXBcqZMA7y0vmYGOTDOQn9PIhtBiT1mVisekrmczvN 5U02f7Qb2Nh+FDN26u1yvntfbyhQPoFYpigKlQRgTsjDg+9LNdQo7pCaarl6kGXHuy8/ u15w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=9edXG9SBCBFkr8z43egDqb7kCES1Ezo7Q/IINFcYamc=; b=Qmsna847eai5h5R6jjXhaN01gRjcqwpQCP5qfiOwKNistvwzFntrlmWT1WKEOeWoki Z6dD6rljgs8j/kkljftBXbt+4wXSQTPfZ+hbcfE3yNV2cVuj+OFXAtHwkGC8DhxCn7zk kISvYLz3mQKgzVBcN0RUnODtg1OyAk+Gcjs659+ghd72V7Usfp7oZWhMzDGiOgxP7ZGy fYftIvqNju5kchuiS81N7k71Bvzq5dVuxAhE945Ubd361eIcxAgF3rlWJvpnmm+amPxC DBF8LdH1qoEyiH2hX453Gi65H6wIKOPxTgL5PasHOe8P0hfYea7v1Kqu66PAs9WNlGSV XLNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id mp41-20020a1709071b2900b0078cffe5dcdesi7035703ejc.451.2022.11.12.18.07.18; Sat, 12 Nov 2022 18:07:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234941AbiKMB1O (ORCPT + 89 others); Sat, 12 Nov 2022 20:27:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41486 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230147AbiKMB1K (ORCPT ); Sat, 12 Nov 2022 20:27:10 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F3FB56307; Sat, 12 Nov 2022 17:27:09 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00A1513D5; Sat, 12 Nov 2022 17:27:16 -0800 (PST) Received: from a077893.arm.com (unknown [10.163.40.190]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1460C3F73D; Sat, 12 Nov 2022 17:27:05 -0800 (PST) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org Cc: Anshuman Khandual , Suzuki K Poulose , James Morse , Jonathan Corbet , Mark Rutland , linux-doc@vger.kernel.org Subject: [PATCH V2 1/2] arm64: Add Cortex-715 CPU part definition Date: Sun, 13 Nov 2022 06:56:44 +0530 Message-Id: <20221113012645.190301-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221113012645.190301-1-anshuman.khandual@arm.com> References: <20221113012645.190301-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add the CPU Partnumbers for the new Arm designs. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: James Morse Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index abc418650fec..4b1ad810436f 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -80,6 +80,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 #define ARM_CPU_PART_NEOVERSE_N2 0xD49 #define ARM_CPU_PART_CORTEX_A78C 0xD4B @@ -142,6 +143,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) -- 2.25.1