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[2620:137:e000::1:20]) by mx.google.com with ESMTP id l17-20020a170906795100b007ae74740f8bsi9272883ejo.386.2022.11.14.10.40.50; Mon, 14 Nov 2022 10:41:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="AABb88/j"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236987AbiKNSdT (ORCPT + 88 others); Mon, 14 Nov 2022 13:33:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236921AbiKNSdL (ORCPT ); Mon, 14 Nov 2022 13:33:11 -0500 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A9892EF6F; Mon, 14 Nov 2022 10:33:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668450790; x=1699986790; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=O4F5TNvwnkr+exXSSQ3fc4AO8Fao7pF9DfMbGT7LQpc=; b=AABb88/jJ2bIZy77vJEaL4Fv3HZFulsvkLXcf9Jk/qoclGjwVzyTTaUG qoLDQURk0kvdYlYkW7ZqB3QIijs5XkV7EGgyyizQfPcwOFkCMji9HCuJy pt7krx9KBxh17+71lYK734c7p5uFZQreAgTEtnpAL/FdOupy6GvvcyCj9 OY4jE5UXKyOXAYL4NQhIU2bPRR2RXQmM/Z5c51VmJhtOP9vm0cpwwFh1F dsGCxnFdOTN07RgRyK2xPVugKO2AtEtDGm3XQE1bKLexKqLd4Pi89IN5u Yyt0hWuMfAWHaKlhJOlfXZ0995QQxWNc9gSBQg251j1KKJJr4sType7Dj Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="299567393" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="299567393" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 10:33:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="616422599" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="616422599" Received: from linux.intel.com ([10.54.29.200]) by orsmga006.jf.intel.com with ESMTP; 14 Nov 2022 10:33:09 -0800 Received: from otcpl-manager.jf.intel.com (otcpl-manager.jf.intel.com [10.54.77.21]) by linux.intel.com (Postfix) with ESMTP id 8487058097C; Mon, 14 Nov 2022 10:33:09 -0800 (PST) From: Gayatri Kammela To: hdegoede@redhat.com Cc: irenic.rajneesh@gmail.com, markgross@kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, sukumar.ghorai@intel.com, xi.pardee@intel.com, rajvi.jingar@intel.com, David E Box Subject: [PATCH v1 2/8] platform/x86: intel/pmc: Move variable declarations and definitions to header and core.c Date: Mon, 14 Nov 2022 10:32:51 -0800 Message-Id: <20221114183257.2067662-3-gayatri.kammela@linux.intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xi Pardee Move the msr_map variable declaration to core.h and move the pmc_lpm_modes definition to core.c. This is a prepartory patch for redesigning the pmc core driver as the variables will be used in multiple PCH specific files. Cc: David E Box Reviewed-by: "David E. Box" Signed-off-by: Xi Pardee Signed-off-by: "David E. Box" --- drivers/platform/x86/intel/pmc/core.c | 15 ++++++++++++++- drivers/platform/x86/intel/pmc/core.h | 13 ++----------- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c index b434cf5b094b..cfa654672cba 100644 --- a/drivers/platform/x86/intel/pmc/core.c +++ b/drivers/platform/x86/intel/pmc/core.c @@ -35,8 +35,21 @@ #define ACPI_S0IX_DSM_UUID "57a6512e-3979-4e9d-9708-ff13b2508972" #define ACPI_GET_LOW_MODE_REGISTERS 1 +/* Maximum number of modes supported by platfoms that has low power mode capability */ +const char *pmc_lpm_modes[] = { + "S0i2.0", + "S0i2.1", + "S0i2.2", + "S0i3.0", + "S0i3.1", + "S0i3.2", + "S0i3.3", + "S0i3.4", + NULL +}; + /* PKGC MSRs are common across Intel Core SoCs */ -static const struct pmc_bit_map msr_map[] = { +const struct pmc_bit_map msr_map[] = { {"Package C2", MSR_PKG_C2_RESIDENCY}, {"Package C3", MSR_PKG_C3_RESIDENCY}, {"Package C6", MSR_PKG_C6_RESIDENCY}, diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h index e64b33e46397..b4279ed59bbe 100644 --- a/drivers/platform/x86/intel/pmc/core.h +++ b/drivers/platform/x86/intel/pmc/core.h @@ -237,17 +237,7 @@ enum ppfear_regs { #define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704 #define ADL_LPM_LIVE_STATUS_OFFSET 0x1764 -static const char *pmc_lpm_modes[] = { - "S0i2.0", - "S0i2.1", - "S0i2.2", - "S0i3.0", - "S0i3.1", - "S0i3.2", - "S0i3.3", - "S0i3.4", - NULL -}; +extern const char *pmc_lpm_modes[]; struct pmc_bit_map { const char *name; @@ -346,6 +336,7 @@ struct pmc_dev { void (*core_configure)(struct pmc_dev *pmcdev); }; +extern const struct pmc_bit_map msr_map[]; void spt_core_init(struct pmc_dev *pmcdev); void cnp_core_init(struct pmc_dev *pmcdev); void icl_core_init(struct pmc_dev *pmcdev); -- 2.34.1