Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   Leo Li <leoyang.li@nxp.com>
To:     Pierre Gondois <pierre.gondois@arm.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
CC:     "Rob.Herring@arm.com" <Rob.Herring@arm.com>,
        Shawn Guo <shawnguo@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        dl-linux-imx <linux-imx@nxp.com>, Chester Lin <clin@suse.com>,
        =?iso-8859-1?Q?Andreas_F=E4rber?= <afaerber@suse.de>,
        Matthias Brugger <mbrugger@suse.com>, dl-S32 <S32@nxp.com>,
        Peng Fan <peng.fan@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
        Sudeep Holla <sudeep.holla@arm.com>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH 07/20] arm64: dts: Update cache properties for freescale
Thread-Topic: [PATCH 07/20] arm64: dts: Update cache properties for freescale
Thread-Index: AQHY7Qn1HioIfePw+0+dxwF9jO4Npq4+66pg
Date:   Mon, 14 Nov 2022 19:55:21 +0000
Message-ID: <AM0PR04MB6289C97297803675DA5A57178F059@AM0PR04MB6289.eurprd04.prod.outlook.com>
References: <20221031091956.531935-1-pierre.gondois@arm.com>
In-Reply-To: <20221031091956.531935-1-pierre.gondois@arm.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?iso-8859-1?Q?Nz80fc8hrfCNrdaX80VmchR5Kz5eEAcZW+PJCSAW95P3g+8tiuq8ldSKU2?=
 =?iso-8859-1?Q?eepTTLBMiVrU06mU7IIu4T3VYPjPjv7hHYeYcBNj1tE9QpIGm3ARA44NYH?=
 =?iso-8859-1?Q?d3CZDJguaRx+r4COa8hqNzUhmmiAZWjX24uwVz87ApCvL4WMrrb4n12KSM?=
 =?iso-8859-1?Q?WU2nC3oK8SdAgofwoksg5dl1y5Rhn3b0FwpT2Mnv+dDkXbuiXwrzJMkUPa?=
 =?iso-8859-1?Q?ABPI0A1PHF/TIwTnR1haM4EY5Svz3DIuvwkhqdmm4XQAgvXvDeDw4vwutj?=
 =?iso-8859-1?Q?mTTFYezL2NUthVj1wl2j4Kmopgk51hw5ZvGWdcH8LQ7sSvTpCWdwoyFwue?=
 =?iso-8859-1?Q?Cb/vZhgYpkYTrtUdRxDRzTQjTiLYKPW0JCc5fDF3BH3HvpAkHCrk9/Onts?=
 =?iso-8859-1?Q?QVkwpU9iPY05WbmqUi1q8Ft7lMR4ICzW2Vsar65ciPPeM/e29Fkqo0pqWR?=
 =?iso-8859-1?Q?9RQ4t3UCfZs8+8P34R8/GabXNwcOCv3lZHAdBjwt7gM7StPeaptMBL680J?=
 =?iso-8859-1?Q?GJPTY/alU65Y1CBs1LdB4GAIrYp6CcO4AML2BqITaw02FGpKQvpDtES28l?=
 =?iso-8859-1?Q?Dt+0hQqr+9kgRwyVYlWkS1Mcaz5fGGAPE1gcrrxCJY4t4d/RMyRbD0Miot?=
 =?iso-8859-1?Q?t47Inpa1mSreOAJDlIaTQG+eBit5wfsrLdumqdqaCtkLT3EEYu1EAqoYka?=
 =?iso-8859-1?Q?hty6bwUjeg9MrrXDBogvJpce+q6Y6ujtezGo1W9kVRXVpltWRPenUDlFsC?=
 =?iso-8859-1?Q?lMedCjrTBiiap/oXlMCzMDwmJzzcEtukEWDaZdZKMsZQ0Hwf/yxX9014G6?=
 =?iso-8859-1?Q?nu0/htboA26zlv/ut7h+wKudCQ1obIeU2iOII3a0sunX+KkuoyAcS8sl/E?=
 =?iso-8859-1?Q?AIoo68cvvQ/FLENKP6o5hqw8FB0NPGoylym0p2FfSnGJXJmBjQ/BfCmlD+?=
 =?iso-8859-1?Q?adQ4iR4V2XgqHpgQfMq6tI1rMlC7zR15gqxsoCIwD486F/KruUK22NmCVr?=
 =?iso-8859-1?Q?GHTnESkKF4Ak+WZfDYcc94v8hqz4/LKPT3j8Wlp6Zp5Xe9dCWuWWd3stVP?=
 =?iso-8859-1?Q?ulfTIYMlw10kj1WobB8O5aeHZdiEx9C9J7CVCGJT0LfiiSZ0OlTfwkqOwB?=
 =?iso-8859-1?Q?gp0VlYdMXd4JXQCgEIJQpyzpmNiniZKd6B6mz4XY23Tq/mSS11K1HjHhtE?=
 =?iso-8859-1?Q?xecwA1yHyzH3WsxgZlK8Lkg5q0TcbLTyg0edjSWpPj01Y21vdShyxk6SAp?=
 =?iso-8859-1?Q?YfTS7TCIY/ivYd2OANP7RKQJ3UN6QaZZe/sGG8oFQeZ5aUejDoj34ZyyzS?=
 =?iso-8859-1?Q?SDvytxc/mg9NXc9+kjxq30hD3zluoaVdLGqfxmDnTLt2IQMVM3V3VHD+eO?=
 =?iso-8859-1?Q?gXnOjDMIaWxzHUfdY1VW7katZES2teTHSALZDRTSFqoVKMddoFcTcQABoj?=
 =?iso-8859-1?Q?YfuTXhlDuYALr8uySou81JcowQWuVd/bvStvkh254WKEJUOfoPWzwjPacd?=
 =?iso-8859-1?Q?nOK/cYEVfvzg9E7D40X9Cwn+DAROf3fDrH4ZH9rPP6hlYfnOseQ+sXTEq/?=
 =?iso-8859-1?Q?8Fr+l+q2Tf+rA/iiko65oTu2tDnDCrN2SGo1CZMxkuOGIYJcblrvrERmNn?=
 =?iso-8859-1?Q?9I8uFou1BNltEaFK0Iqu21foLLkbwc5G4o?=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB6289.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: d809e196-6196-45d9-2297-08dac67a2995
X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Nov 2022 19:55:21.1670
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: DJz8kqPd3qq8XmpNB4VGwGncWin3g3annhJwjo8D1HwOUc8CSYOWur35AE5AcOIGDn5rdc969AJLUMNXK0VRvQ==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR04MB7080
X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE,
        RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham
        autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org


> -----Original Message-----
> From: Pierre Gondois <pierre.gondois@arm.com>
> Sent: Monday, October 31, 2022 4:20 AM
> To: linux-kernel@vger.kernel.org
> Cc: pierre.gondois@arm.com; Rob.Herring@arm.com; Shawn Guo
> <shawnguo@kernel.org>; Leo Li <leoyang.li@nxp.com>; Rob Herring
> <robh+dt@kernel.org>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@linaro.org>; Sascha Hauer
> <s.hauer@pengutronix.de>; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; dl-linux-
> imx <linux-imx@nxp.com>; Chester Lin <clin@suse.com>; Andreas F=E4rber
> <afaerber@suse.de>; Matthias Brugger <mbrugger@suse.com>; dl-S32
> <S32@nxp.com>; Peng Fan <peng.fan@nxp.com>; Jacky Bai
> <ping.bai@nxp.com>; Sudeep Holla <sudeep.holla@arm.com>; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org
> Subject: [PATCH 07/20] arm64: dts: Update cache properties for freescale
>=20
> The DeviceTree Specification v0.3 specifies that the cache node 'compatib=
le'
> and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
>=20
> The recently added init_of_cache_level() function checks these properties=
.
> Add them if missing.
>=20
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>

Acked-by: Li Yang <leoyang.li@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++
> arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++
>  arch/arm64/boot/dts/freescale/imx8ulp.dtsi     | 1 +
>  arch/arm64/boot/dts/freescale/s32g2.dtsi       | 2 ++
>  arch/arm64/boot/dts/freescale/s32v234.dtsi     | 2 ++
>  8 files changed, 16 insertions(+)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 5627dd7734f3..ed0cc1a5d17e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -46,6 +46,7 @@ cpu1: cpu@1 {
>=20
>  		l2: l2-cache {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> index ca3d5a90d6d4..c8b1202d2584 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
> @@ -83,6 +83,7 @@ cpu3: cpu@3 {
>=20
>  		l2: l2-cache {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> index feab604322cf..4590bdc076b7 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
> @@ -78,6 +78,7 @@ cpu3: cpu@3 {
>=20
>  		l2: l2-cache {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> index 6f6667b70028..2a7e13b6ef8a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
> @@ -95,18 +95,22 @@ cpu7: cpu@301 {
>=20
>  	cluster0_l2: l2-cache0 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster1_l2: l2-cache1 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster2_l2: l2-cache2 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster3_l2: l2-cache3 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	CPU_PW20: cpu-pw20 {
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> index c3dc38188c17..c12c86915ec8 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
> @@ -95,18 +95,22 @@ cpu7: cpu@301 {
>=20
>  	cluster0_l2: l2-cache0 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster1_l2: l2-cache1 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster2_l2: l2-cache2 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	cluster3_l2: l2-cache3 {
>  		compatible =3D "cache";
> +		cache-level =3D <2>;
>  	};
>=20
>  	CPU_PW20: cpu-pw20 {
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 60c1b018bf03..187353458673 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -50,6 +50,7 @@ A35_1: cpu@1 {
>=20
>  		A35_L2: l2-cache0 {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 824d401e7a2c..d8c82da88ca0 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -52,10 +52,12 @@ cpu3: cpu@101 {
>=20
>  		cluster0_l2: l2-cache0 {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>=20
>  		cluster1_l2: l2-cache1 {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> diff --git a/arch/arm64/boot/dts/freescale/s32v234.dtsi
> b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> index ba0b5305d481..3e306218d533 100644
> --- a/arch/arm64/boot/dts/freescale/s32v234.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32v234.dtsi
> @@ -61,10 +61,12 @@ cpu3: cpu@101 {
>=20
>  		cluster0_l2_cache: l2-cache0 {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>=20
>  		cluster1_l2_cache: l2-cache1 {
>  			compatible =3D "cache";
> +			cache-level =3D <2>;
>  		};
>  	};
>=20
> --
> 2.25.1