Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp6379901rwb; Mon, 14 Nov 2022 19:42:42 -0800 (PST) X-Google-Smtp-Source: AA0mqf57vLS8TOXxzimJeBareUjUl+s1lQa5B+XBIiDHrnkHrsW6TAsR/UECsba6gcLsYmRrjHBO X-Received: by 2002:a17:906:3c9:b0:7af:a2d4:e95c with SMTP id c9-20020a17090603c900b007afa2d4e95cmr1345182eja.666.1668483762674; Mon, 14 Nov 2022 19:42:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668483762; cv=none; d=google.com; s=arc-20160816; b=Z0mzuDbGWKtmmtVWeNZez/s6+6tUOcjC5k6ll7vgYKFCcQ9Pj+MvBBdck1ixtVZqDd zrta0YPof6YaRAasWMD5HQ+ryOAo0aT3ZIPHEWNyBBc+8eteX4Vns141rdlyNxk+h+IH y5H+KF7YZsr19FuQQVf1A9/7aMT9gPq89BUPJmNN5l0yZTtMT+quqtjO6JpJ+crjhI9g oY6iLrdYu26GF1dAf5tk4IULnSOr22NUvOfoolJ0CBL0byIFol/BkDGJjN/Hu4RZzQHw apGS9EaDoZIwqisW6l8i8QnSvJq3vICX3Wk1kNnKNYzLoO6au6Hviog8uCvEDKNM99Hy ydUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=M20gL2RmftjzyJWarcZB65UxIvlkmxEk/MaGwQurIsI=; b=t4+4MqIA1iQQ1k1YfLj78Y6qnD2aqICK+GMRMEUiP8UxbBy73pUACeOjpYp1W2V4g/ vNesSsyIh23ur4Ue7KBeGQD9hq/C3PiIHP8xLSCV9dhg+fS5MFI9ivfvVslHONstf/Ms RefKtSRczl/aonmIcMyHZB58eMDibmqnNWYqs3+3S2UlMVR9DWVA5e+qgZXJEDU7gSs+ J6yjwJ6H1+dUEGn/P5tfgHdPDUc40+77E/kEGScdhXoY6LoWAMe0daJ65//DYdPtp3Yk Rv7CjHFZ1wUfNuAS+amgGk9ORqEzAKMp3UfPLDekdfb4LSaAJkzTdkQZQBcBj2Rt90LW VZkw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id js6-20020a17090797c600b0078dffe01cbesi11680087ejc.4.2022.11.14.19.42.21; Mon, 14 Nov 2022 19:42:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232135AbiKODNG (ORCPT + 88 others); Mon, 14 Nov 2022 22:13:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231950AbiKODMy (ORCPT ); Mon, 14 Nov 2022 22:12:54 -0500 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53880DF47 for ; Mon, 14 Nov 2022 19:12:51 -0800 (PST) X-ASG-Debug-ID: 1668481969-1eb14e7e6489960001-xx1T2L Received: from ZXSHMBX2.zhaoxin.com (ZXSHMBX2.zhaoxin.com [10.28.252.164]) by mx2.zhaoxin.com with ESMTP id kWOIIZDAWmtr9SHg (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Tue, 15 Nov 2022 11:12:49 +0800 (CST) X-Barracuda-Envelope-From: LeoLiu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX2.zhaoxin.com (10.28.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:48 +0800 Received: from localhost.localdomain (10.32.64.1) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 15 Nov 2022 11:12:45 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: LeoLiu-oc X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , , , , , , , , , , , , CC: , , , leoliu-oc Subject: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Date: Tue, 15 Nov 2022 11:12:44 +0800 X-ASG-Orig-Subj: [PATCH v2 3/5] ACPI/PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge Message-ID: <20221115031244.1667093-1-LeoLiu-oc@zhaoxin.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-Originating-IP: [10.32.64.1] X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1668481969 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 1313 X-Barracuda-BRTS-Status: 1 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0273 1.0000 -1.8440 X-Barracuda-Spam-Score: -1.84 X-Barracuda-Spam-Status: No, SCORE=-1.84 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.102147 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: leoliu-oc Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: leoliu-oc --- include/uapi/linux/pci_regs.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..37f3baa336d7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -799,6 +799,11 @@ #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ +/* PCIe advanced error reporting extended capabilities for PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* Secondary Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* Secondary Uncorrectable Error Severit */ +#define PCI_ERR_CAP2 0x38 /* Secondary Advanced Error Capabilities */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ -- 2.20.1