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From:   Biju Das <biju.das.jz@bp.renesas.com>
To:     Geert Uytterhoeven <geert@linux-m68k.org>
CC:     Prabhakar <prabhakar.csengg@gmail.com>,
        Wim Van Sebroeck <wim@linux-watchdog.org>,
        Guenter Roeck <linux@roeck-us.net>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        "linux-watchdog@vger.kernel.org" <linux-watchdog@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-renesas-soc@vger.kernel.org" 
        <linux-renesas-soc@vger.kernel.org>,
        Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put the PM
 clocks
Thread-Topic: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put the PM
 clocks
Thread-Index: AQHY+FQ3i7+8G/jXAEWaK/AAUJtKua4+wHcggAAGgYCAAAGLYIAA0q6wgAAHxICAAAQu4A==
Date:   Tue, 15 Nov 2022 08:28:24 +0000
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> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 15 November 2022 08:11
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Prabhakar <prabhakar.csengg@gmail.com>; Wim Van Sebroeck
> <wim@linux-watchdog.org>; Guenter Roeck <linux@roeck-us.net>; Philipp
> Zabel <p.zabel@pengutronix.de>; linux-watchdog@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Fabrizio
> Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Subject: Re: [PATCH] watchdog: rzg2l_wdt: Issue a reset before we put
> the PM clocks
>=20
> Hi Biju,
>=20
> On Tue, Nov 15, 2022 at 8:48 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > > -----Original Message-----
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Mon, Nov 14,
> > > > 2022 at 7:42 PM Biju Das
> > > <biju.das.jz@bp.renesas.com> wrote:
> > > > > > From: Prabhakar <prabhakar.csengg@gmail.com> On RZ/Five SoC
> it
> > > > > > was observed that setting timeout (to say 1
> > > sec)
> > > > > > wouldn't reset the system. To fix this we make sure we issue
> a
> > > > > > reset before putting the PM clocks to make sure the
> registers
> > > have
> > > > > > been
> > > > cleared.
> > > > > >
> > > > > > While at it re-used rzg2l_wdt_stop() in
> > > > > > rzg2l_wdt_set_timeout()
> > > as
> > > > > > we were calling the same functions here.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > > Note,
> > > > > > - This patch has been tested on RZ/G2L, RZ/V2M and RZ/Five.
> > > > > > - My initial investigation showed adding the delay after
> > > > > > pm_runtime_get_sync()
> > > > > >   also fixed this issue.
> > > > > > - Do I need add the fixes tag ? what should be the operation
> > > PUT-
> > > > > > >RESET/RESET->PUT?
> > > > >
> > > > > It looks like timing issue, None of the previous devices are
> > > > > affected by
> > > > this.
> > > >
> > > > To me it looks like the device must be clocked for the reset
> > > > signal
> > > to
> > > > be propagated?
> > >
> > > Yep, provide clk supply for a device, then apply reset.
> >
> > Maybe we need to make it consistent by taking care of  [1]
> >
> > Current patch: CLK ON -> apply Reset for V2M.
> > [1]:  Apply Reset -> CLK ON for V2M.
>=20
> Yes, that would also simplify that patch: just add the call to reset?

Fabrizio previously told me, CLK ON -> apply Reset does not work for RZ/V2M=
 reboot use case.

Regards,
Biju