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Message-ID: <c30c0068-de5d-b3ab-9b05-5153ad8c4b3d@linaro.org>
Date:   Tue, 15 Nov 2022 17:40:17 +0100
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Subject: Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: add yaml for
 LoongArch CPU interrupt controller
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To:     Liu Peibao <liupeibao@loongson.cn>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Huacai Chen <chenhuacai@kernel.org>,
        WANG Xuerui <kernel@xen0n.name>
Cc:     Jianmin Lv <lvjianmin@loongson.cn>,
        Yinbo Zhu <zhuyinbo@loongson.cn>,
        wanghongliang <wanghongliang@loongson.cn>,
        linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20221114113824.1880-1-liupeibao@loongson.cn>
 <20221114113824.1880-3-liupeibao@loongson.cn>
From:   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
In-Reply-To: <20221114113824.1880-3-liupeibao@loongson.cn>
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On 14/11/2022 12:38, Liu Peibao wrote:
> Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how
> the 14 IRQs are wired to the platform's internal interrupt controller by
> devicetree.
> 
> Signed-off-by: Liu Peibao <liupeibao@loongson.cn>
> ---


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof