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b=7ihGthdN7C32ppdrEbrJHTAQeM1lGRdU1LyQ02F9T7RpzySsZ/5MzQpcIVRcaaNI+x RI+kv5PGSBRrmrrArISgWGCUfGDnjv/+9ozdoHbCBoBmmEe3BCWAQAZAxq0590ouL0Np Y2Qr3NeoEccWh1I9O/rkDr4QZhMh+AG7/geXyrjy3SMcQYrC1TiI5NxByB7PUtM+LSvJ Ev+jQr1TaGBEfvy1iHM3AZXWbsUZCgp5x7iH+eyRjDbcVbJhG2eaj17KC9N6HKTo8kbo +dVoi1d+H7p/I/s+ULe00Md2aUFgvGffwQlPs1qR2YQLFGH5AZMzTPfDPyil1N+0Swr4 4mfQ== X-Gm-Message-State: ANoB5plhuvMlobC6CkvlojWK8Ubjo93JNjZhFQ7Zk+gaAdPGrKjW/w4P 9/3o4I7LBtN9E/VV0FyiXbg2S/3tq/aWyZMMQyw= X-Received: by 2002:a17:90a:de96:b0:214:132a:2b90 with SMTP id n22-20020a17090ade9600b00214132a2b90mr1482901pjv.195.1668533081732; Tue, 15 Nov 2022 09:24:41 -0800 (PST) MIME-Version: 1.0 References: <20221115162654.2016820-1-frieder@fris.de> In-Reply-To: <20221115162654.2016820-1-frieder@fris.de> From: Fabio Estevam Date: Tue, 15 Nov 2022 14:24:24 -0300 Message-ID: Subject: Re: [PATCH v2] spi: spi-imx: Fix spi_bus_clk if requested clock is higher than input clock To: Frieder Schrempf Cc: David Jander , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, Marc Kleine-Budde , Mark Brown , Sascha Hauer , Shawn Guo , Frieder Schrempf , Marek Vasut , stable@vger.kernel.org, Baruch Siach , Minghao Chi , NXP Linux Team , Pengutronix Kernel Team Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 15, 2022 at 1:27 PM Frieder Schrempf wrote: > > From: Frieder Schrempf > > In case the requested bus clock is higher than the input clock, the correct > dividers (pre = 0, post = 0) are returned from mx51_ecspi_clkdiv(), but > *fres is left uninitialized and therefore contains an arbitrary value. > > This causes trouble for the recently introduced PIO polling feature as the > value in spi_imx->spi_bus_clk is used there to calculate for which > transfers to enable PIO polling. > > Fix this by setting *fres even if no clock dividers are in use. > > This issue was observed on Kontron BL i.MX8MM with an SPI peripheral clock set > to 50 MHz by default and a requested SPI bus clock of 80 MHz for the SPI NOR > flash. > > With the fix applied the debug message from mx51_ecspi_clkdiv() now prints the > following: > > spi_imx 30820000.spi: mx51_ecspi_clkdiv: fin: 50000000, fspi: 50000000, > post: 0, pre: 0 > > Fixes: 07e759387788 ("spi: spi-imx: add PIO polling support") > Cc: Marc Kleine-Budde > Cc: David Jander > Cc: Fabio Estevam > Cc: Mark Brown > Cc: Marek Vasut > Cc: stable@vger.kernel.org > Signed-off-by: Frieder Schrempf Thanks for the fix: Tested-by: Fabio Estevam