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From:   Alex Helms <alexander.helms.jy@renesas.com>
To:     linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-clk@vger.kernel.org
Cc:     krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
        sboyd@kernel.org, mturquette@baylibre.com, geert+renesas@glider.be,
        alexander.helms.jy@renesas.com
Subject: [PATCH 0/2] Add support for Renesas PhiClock 9FGV1006 clock generator
Date:   Tue, 15 Nov 2022 12:26:23 -0700
Message-Id: <20221115192625.9410-1-alexander.helms.jy@renesas.com>
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Device tree bindings and a common clock framework device driver for
the Renesas PhiClock 9FGV1006 clock generator.

Alex Helms (2):
  dtbindings: clock: Add bindings for Renesas PhiClock
  clk: Add support for Renesas PhiClock clock generator

 .../bindings/clock/renesas,phiclock.yaml      |  81 ++
 MAINTAINERS                                   |   6 +
 drivers/clk/Kconfig                           |   9 +
 drivers/clk/Makefile                          |   1 +
 drivers/clk/clk-phiclock.c                    | 729 ++++++++++++++++++
 5 files changed, 826 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,phiclock.yaml
 create mode 100644 drivers/clk/clk-phiclock.c


base-commit: 094226ad94f471a9f19e8f8e7140a09c2625abaa
-- 
2.25.1