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[209.85.219.176]) by smtp.gmail.com with ESMTPSA id ay42-20020a05622a22aa00b0039a08c0a594sm8399285qtb.82.2022.11.16.01.04.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Nov 2022 01:04:04 -0800 (PST) Received: by mail-yb1-f176.google.com with SMTP id e68so17362527ybh.2; Wed, 16 Nov 2022 01:04:04 -0800 (PST) X-Received: by 2002:a25:258d:0:b0:6ca:3b11:8d76 with SMTP id l135-20020a25258d000000b006ca3b118d76mr20609898ybl.202.1668589444351; Wed, 16 Nov 2022 01:04:04 -0800 (PST) MIME-Version: 1.0 References: <20221115105135.1180490-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221115105135.1180490-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 16 Nov 2022 10:03:53 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/3] riscv: dts: renesas: r9a07g043f/rzfive-smarc-som: Enable ADC/OPP/Thermal Zones/TSU To: Prabhakar Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Magnus Damm , Conor Dooley , Krzysztof Kozlowski , Rob Herring , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Tue, Nov 15, 2022 at 11:51 AM Prabhakar wrote: > From: Lad Prabhakar > > Enable support for below blocks found on RZ/Five SMARC EVK SoC/SoM: > - ADC > - OPP > - Thermal Zones > - TSU > > Note, these blocks are enabled in RZ/G2UL SMARC SoM DTSI [0] hence > deleting these disabled nodes from RZ/Five SMARC SoM DTSI enables them > here too as we include [0] in RZ/Five SMARC SoM DTSI. > > [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi > > Signed-off-by: Lad Prabhakar Thanks for your patch! > --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi > @@ -16,13 +16,6 @@ aliases { > chosen { > bootargs = "ignore_loglevel"; > }; > - > - /delete-node/opp-table-0; > - /delete-node/thermal-zones; > -}; > - > -&adc { > - status = "disabled"; I believe this is not sufficient to enable the ADC, as it is disabled by default? So this needs to set the status to "okay" and configure pin control, depending on SW_SW0_DEV_SEL, just like in arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi? The rest LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds