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From:   Rahul Tanwar <rtanwar@maxlinear.com>
To:     <devicetree@vger.kernel.org>, <robh@kernel.org>,
        <andriy.shevchenko@linux.intel.com>, <tglx@linutronix.de>,
        <mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>,
        <x86@kernel.org>
CC:     <linux-kernel@vger.kernel.org>, <hpa@zytor.com>,
        <alan@lxorguk.ukuu.org.uk>, <dirk.brandewie@gmail.com>,
        <grant.likely@secretlab.ca>, <sodaville@linutronix.de>,
        <devicetree-discuss@lists.ozlabs.org>,
        <linux-lgm-soc@maxlinear.com>,
        "Rahul Tanwar" <rtanwar@maxlinear.com>
Subject: [PATCH v2 0/2]  x86/of: Fix a bug in x86 arch OF support
Date:   Wed, 16 Nov 2022 18:28:19 +0800
Message-ID: <cover.1668589253.git.rtanwar@maxlinear.com>
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+ devicetree@vger.kernel.org

Hi Sebastian,

All touched part in this patch series was added by you. Hoping for
concerns/comments or best case ACK, reviewed-by tag from you.
I have CCed all others who were involved with you when you added
this changes.

Hi devicetree@vger.kernel.org, Rob,

Since this appears to be entrirely in devicetree domain. Hoping
for feedback, concerns, mistakes or improvement feedbacks from
you.

Hi Andy,

Hoping for a reviewed-by tag from you once you think it is ready
to go. Thanks.


Hi Thomas, Ingo, Boris, Andy, Dave & all x86@kernel.org maintainers,

Resending below details hoping to figure out if the changes are
logically aligned with your understanding & that it will not break
any x86/arch concerns that you might have. Shooting on any mistakes
welcomed :-).


I sent this patch 3 times but for some reasons, never got any response or
attention from anybody so far. Hence, resending with a cover letter to
explain the rationale behind it in detail & to justify the need to add
this fix. Also, hoping to get some feedback in-case i am mistaken in my
understanding which might be the reason why i never got any response.

Background (baseline understanding - pls correct if mistaken anywhere):

References [1], [2] & [6]

For SMP systems, Intel defines three (logically four) interrupt modes
during boot/init time while BIOS/bootloader boots & switches to linux
kernel.

  1. PIC mode - Legacy 8259 PIC interrupt controller.
  2. Virtual wire mode via Local APIC - uses local APIC as virtual wire
  3. Virtual wire mode via I/O APIC - uses I/O APIC as virtual wire
  4. Symmetric I/O mode - final one used by linux for SMP systems.=20

BIOS/bootloaders are supposed to boot in either #1 or #2 or #3 and then
switch to #4 in linux for SMP systems.

For our platform, we use #2.

Detection of which interrupt mode the system is booting in is made by using
below global variable in apic.c

int pic_mode __ro_after_init;=20

Here pic_mode =3D 1 means #1 (PIC mode) above.
And pic_mode =3D 0 means #2 or #3 (basically virtual wire mode via apic).

And apic.c while doing setup_local_APIC() uses below code [3]:

        value =3D apic_read(APIC_LVT0) & APIC_LVT_MASKED;
        if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
                value =3D APIC_DM_EXTINT;
                apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu=
);
        } else {
                value =3D APIC_DM_EXTINT | APIC_LVT_MASKED;
                apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu)=
;
        }
        apic_write(APIC_LVT0, value);

What i understand from above is that if at this point of time, as long as
it is cpu0 & pic_mode=3D1, it will set delivery mode to ExtINT (causes the
processor to respond to the interrupt as if the interrupt originated in an
externally connected (8259A-compatible) interrupt controller) and enables/
unmask the interrupts.

pic_mode is presently set/populated/initialized at only two places:
 1. In  mpparse.c [4]
 2. In devicetree.c [7]

For #1 MPPARSE Kconfig definition is as below:

=09config X86_MPPARSE
        =09bool "Enable MPS table" if ACPI
        =09default y
        =09depends on X86_LOCAL_APIC
        =09help
          =09For old smp systems that do not have proper acpi support. Newe=
r systems
          =09(esp with 64bit cpus) with acpi support, MADT and DSDT will ov=
erride it

As seen above, if ACPI is not enabled, then mpparse by default is always
enabled. Presently, there is no way to disable MPPARSE (if ACPI is not
enabled). This to me appears to be another bug which needs fixing. As per
theory, MPPARSE was to support MPS spec [1] as a temporary solution to
support SMP systems until a final ACPI standard was added. But now if ACPI
is not enabled, it will rely on MPPARSE driver to read MP floating pointer
structure's IMCRP Bit 7 of MP feature info byte 2 [5] to figure out if it
supports PIC mode or virtual wire mode and initialize pic_mode variable
accordingly. If ACPI is enabled, the ACPI code overrides it by using the
MADT table spec'ed in ACPI spec [2].=20

For #2 devicetree.c presently hardcodes pic_mode =3D 1 (PIC Mode). There is
no support to configure virtual wire mode via devicetree path for OF based
systems.

Now we have a platform which is OF based & does not use legacy 8259 PIC
interrupt controller. Non ACPI compliant as well as non MPPARSE compliant.

For such platforms, it appears to me that hardcoding pic_mode =3D 1 (PIC Mo=
de)
and giving no other choice to choose virtual wire mode is a bug for OF
based x86 platforms.=20

Just like mpparse relies on IMCRP bit 7 of MP feature info byte2 [5] to
select pic_mode to PIC mode or virtual wire mode. arch/x86/kernel/devicetre=
e.c
should also provide some similar configurability to choose interrupt
delivery mode & not hardcode it to PIC mode.

This patch is to fix above explained bug in x86/of support for interrupt
delivery mode configuration. Please let me know if you find any mistake
in above understanding or if you have a alternative better suggestion to
solve it or if you find anything odd here in our platform/system. TIA.

The patch is baselined on below git tree:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core

[1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/MPspec.pdf
[2] https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
[3] https://elixir.bootlin.com/linux/v6.1-rc5/source/arch/x86/kernel/apic/a=
pic.c#L1691
[4] https://elixir.bootlin.com/linux/v6.1-rc5/source/arch/x86/kernel/mppars=
e.c#L517
[5] https://www.manualslib.com/manual/77733/Intel-Multiprocessor.html?page=
=3D40#manual
[6] https://www.intel.com/content/www/us/en/developer/articles/technical/in=
tel-sdm.html
[7] https://elixir.bootlin.com/linux/v6.1-rc5/source/arch/x86/kernel/device=
tree.c#L170

v2:
- Address review concern from Andy - rename property name to make
  it a bit more positive & self explanatory.
- Found that the bindings document for these HW's (APIC) are a bit
  off/obsolete and still in text format. Created new YAML schemas
  one for each - lapic & ioapic. Updated these schemas with latest
  info and add in new optional property details in the updated
  schema for lapic. Delete/let go of the text binding doc.
- CC devicetree@vger.kernel.org as these changes appear to be
  mainly targeted for devicetree maintainers review & approval.
- Increase CCed list to include all possible people who touched
  and were involved this part of code/feature addition.

v1:
- Initial draft


Rahul Tanwar (2):
  x86/of: Add support for boot time interrupt delivery mode
    configuration
  x86/of: Convert & update Intel's APIC related binding schemas

 .../intel,ce4100-ioapic.txt                   | 26 --------
 .../intel,ce4100-ioapic.yaml                  | 62 ++++++++++++++++++
 .../intel,ce4100-lapic.yaml                   | 63 +++++++++++++++++++
 arch/x86/kernel/devicetree.c                  |  9 ++-
 4 files changed, 133 insertions(+), 27 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/=
intel,ce4100-ioapic.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/=
intel,ce4100-ioapic.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/=
intel,ce4100-lapic.yaml

--=20
2.17.1