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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB2401.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: dcdb77af-c015-49fa-84d7-08dac8348038 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Nov 2022 00:41:44.0920 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: UAFe6nV6Rn1K+tK+6g6nWT5BvgKtqQORuocktmc7piXfBnfONGF713gyEyEjIY2E X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6971 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [AMD Official Use Only - General] From: Rob Herring Sent: Wednesday, November 16, 2022 2:30 PM >> v8: >> - Apply review request changes and picked the two unique examples >> for the 4 chip-selects as one has the reset control support and >> the other an interrupt. Missed the --in-reply-to in git >> send-email for v7, included in this update. > >No, you haven't. By default in git, you don't have to do anything. See >--thread and --no-chain-reply-to options. If you are messing with >--in-reply-to, you are doing it wrong. > >Please resend the whole series properly threaded. Will resend the series >> diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.y= aml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> new file mode 100644 >> index 000000000000..622c93402a86 >> --- /dev/null > +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml >> @@ -0,0 +1,60 @@ ... >> + >> +title: AMD Pensando Elba SoC Resource Controller >> + >> +description: | >> + AMD Pensando Elba SoC Resource Controller functions are >> + accessed with four chip-selects. Reset control is on CS0. > > One device with 4 chip-selects? Then I'd expect 'reg =3D <0 1 2 3>;' > > Hard to say more because I don't have the whole thread nor remember what > exactly we discussed before. That was 100s of bindings ago... I agree and the example for v7 had all 4 chip-selects shown. This is not a= pick and choose device on what functions to use for a usable system. Krzysztof requ= ested only showing two chip-selects in the example. ... >> +examples: >> + - | >> + #include >> + >> + spi { >> + #address-cells =3D <1>; >> + #size-cells =3D <0>; >> + num-cs =3D <4>; >> + >> + system-controller@0 { >> + compatible =3D "amd,pensando-elbasr"; >> + reg =3D <0>; >> + spi-max-frequency =3D <12000000>; >> + #reset-cells =3D <1>; >> + }; >> + >> + system-controller@2 { >> + compatible =3D "amd,pensando-elbasr"; >> + reg =3D <2>; >> + spi-max-frequency =3D <12000000>; >> + interrupt-parent =3D <&porta>; >> + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; >> + }; >> + }; Regards, Brad