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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM5PR1101MB2172.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 03a2a8bc-1392-4634-41fb-08dac84d1478 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Nov 2022 03:37:40.7652 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 55OuwNiX8/qepFbN2iDSEyYCu8IL2sgRjaBEnDNFPEsfr7D+/P3Ch64zou4DqxOQ5LXoy8maX1GrwRB0aoqvRw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR11MB7647 X-OriginatorOrg: intel.com X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > > > > But what about NMIs, afaict this is all horribly broken for NMIs. > > > > > > > > > > So the whole VMX thing latches the NMI (which stops NMI > > > > > recursion), > > > right? > > > > > > > > > > But then you drop out of noinstr code, which means any random > > > > > exception can happen (kprobes #BP, hw_breakpoint #DB, or even > > > > > #PF due to random nonsense like *SAN). This exception will do > > > > > IRET and clear the NMI latch, all before you get to run any of th= e NMI > code. > > > > > > > > What you said here implies that we have this problem in the existin= g > code. > > > > Because a fake iret stack is created to call the NMI handler in > > > > the IDT NMI descriptor, which lastly executes the IRET instruction. > > > > > > I can't follow; of course the IDT handler terminates with IRET, it ha= s to no? > > > > With FRED, ERETS/ERETU replace IRET, and use bit 28 of the popped CS > > field to control whether to unblock NMI. If bit 28 of the field (above > > the selector) is 1, ERETS/ERETU unblocks NMIs. >=20 > Yes, I know that. It is one of the many improvements FRED brings. > Ideally the IBT WAIT-FOR-ENDBR state also gets squirreled away in the > hardware exception frame, but that's still up in the air I believe :/ >=20 > Anyway.. given there is interrupt priority and NMI is pretty much on top = of > everything else the reinject crap *should* run NMI first. That way NMI ru= ns > with the latch disabled and whatever other pending interrupts will run la= ter. >=20 > But that all is still broken because afaict the current code also leaves = noinstr -- > and once you leave noinstr (or use a static_key, static_call or anything = else that > *can* change at runtime) you can't guarantee nothing. For NMI, HPA asked me to use "int $2", as it switches to the NMI IST stack = to execute the NMI handler, essentially like how HW deals with a NMI in host. = and I tested it with NMI watchdog, it looks working fine. For IRQs, we still use the dispatch table, but with a new func added in DEFINE_IDTENTRY_SYSVEC with the noinstr entry/exit code removed: #define DEFINE_IDTENTRY_SYSVEC(func) \ static void __##func(struct pt_regs *regs); \ \ __visible noinstr void func(struct pt_regs *regs) \ { \ irqentry_state_t state =3D irqentry_enter(regs); \ \ instrumentation_begin(); \ kvm_set_cpu_l1tf_flush_l1d(); \ run_sysvec_on_irqstack_cond(__##func, regs); \ instrumentation_end(); \ irqentry_exit(regs, state); \ } \ \ +void dispatch_table_##func(struct pt_regs *regs) \ +{ \ + kvm_set_cpu_l1tf_flush_l1d(); \ + run_sysvec_on_irqstack_cond(__##func, regs); \ +} + \ \ static noinline void __##func(struct pt_regs *regs) How do you think?