Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp1844261rwb; Thu, 17 Nov 2022 02:57:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf4vA10j4Qk7QuCOAlCTwWInwAeZEthcRU1/5ZRuFm+2Aw7w3I/pqK2ffUlnw1TiqCEDsJUA X-Received: by 2002:a17:906:2552:b0:7ad:917b:61ec with SMTP id j18-20020a170906255200b007ad917b61ecmr1687072ejb.513.1668682627810; Thu, 17 Nov 2022 02:57:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668682627; cv=none; d=google.com; s=arc-20160816; b=SELbNTcerENFfEwX0BgrfG7HBpb9wh3EDIErz2nGcVCqoGbCfOir689Gf0R541HfzS FWu0Zjdkvkoql9GgJD6K6oVfsHh8vmPJhauNEHmdNAZaAr5q7vTd4rE3lX40mn67qITP 9E6tAh8PE2Be/cmKnx0vJ7HeEkQaxLGaLjLcJ+b8yTUvfEPJ8qiKGdX8/5G3aY3pZKzd veVCROHVh9YwCGNPNqDwBjN1Gf7M1LdHB06rJG2GCvj3RgiqNmKdp0z0OalnwTwWc9OW KmJA8TDgHUR64gwQXGXyn0AgJBVSWnTrW141HDnOaR0Iv5G9Bc4iZ/z1lcqsOGptAk+/ nJ0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GDE8ClJ6PkxhwVCALsq32DTIjfDnSooH/tbirMBUgaw=; b=jQnLxvEk9uwwmunzCrueElf54N9pxF97f5ImDxi40yKD5eGW7LU6cwAJcCcNJkKJBb 3+rRBDmAER7cRkd3fd8wyKmLzauUut24VwVqrUc0lT031g18liQr5vLZqM6hiqEwDr80 Jod2glBu+RYBfacJ7eIn9CHFpb4mzoM4NcVqBVcS1stt7YSSmejmRyJt8vQ+jLKibBSJ 6gbgs0M9dAbR3YyR7D7byyoeil6DXpPLG2JNJlynST41Rw23yuIjyM86BOCUUW7dmptl k/dA/FoecM8yo8VTSx1W8T2HXiuY+Tg1AnoKqGOvJQsFU/1fHd/WNLO1/AVs35Ky+bk9 D2oQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="ZyH/St2N"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id dt17-20020a170907729100b007317ad1f9a4si317648ejc.310.2022.11.17.02.56.46; Thu, 17 Nov 2022 02:57:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b="ZyH/St2N"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239690AbiKQKyU (ORCPT + 91 others); Thu, 17 Nov 2022 05:54:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239524AbiKQKxR (ORCPT ); Thu, 17 Nov 2022 05:53:17 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EFC165B5AD; Thu, 17 Nov 2022 02:53:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1668682391; x=1700218391; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=V+B/oow35dGgcpcT99slHtwXN+81/1x8fB2BGyRH3ZM=; b=ZyH/St2Np4muxa8WcdPP+tqUDbW62bytbVIg57RPAfYBLXX4nOwXB0NJ 98RvqoA+csqF0/mhcogdD6+gdI5VSrS9GiQshykWWp78cV5dsjUf80cLg RXJlaY/gkPvgYCz2yITrX0HwF6qkMvRGJhJycK5C8cFcDVJLaw9QmWCmF i/txwxacyY15VENiIUq5IifkFfReoygh458Uot6roxbJpjoerwJy0hbUI w/H81gb2AtxluaP0KxT9Fc8PEIuINrmLRmHNcwGDX7tO8ZF/4+LH2mvcZ CDHNOrTRzk792uGMKik/AEfTtNY2+tGhHrNLPiaZof11SoYcTqYvEpco7 g==; X-IronPort-AV: E=Sophos;i="5.96,171,1665471600"; d="scan'208";a="189356168" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Nov 2022 03:53:11 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 17 Nov 2022 03:53:08 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 17 Nov 2022 03:53:06 -0700 From: Tudor Ambarus To: , , , , , CC: , , , , , Tudor Ambarus Subject: [PATCH 5/8] ARM: dts: at91-sama5d27_wlsom1: Set sst26vf064b SPI NOR flash at its maximum frequency Date: Thu, 17 Nov 2022 12:52:46 +0200 Message-ID: <20221117105249.115649-6-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117105249.115649-1-tudor.ambarus@microchip.com> References: <20221117105249.115649-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org sama5d27-wlsom1 populates an sst26vf064b SPI NOR flash. Its maximum operating frequency for 2.7-3.6V is 104 MHz. As the flash is operated at 3.3V, increase its maximum supported frequency to 104MHz. The increasing of the spi-max-frequency value requires the setting of the "CE# Not Active Hold Time", thus set the spi-cs-setup-ns to a value of 7. The sst26vf064b datasheet specifies just a minimum value for the "CE# Not Active Hold Time" and it advertises it to 5 ns. There's no maximum time specified. I determined experimentally that 5 ns for the spi-cs-setup-ns is not enough when the flash is operated close to its maximum frequency and tests showed that 7 ns is just fine, so set the spi-cs-setup-ns dt property to 7. With the increase of frequency the reads are now faster with ~37%. Signed-off-by: Tudor Ambarus --- arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi index 83bcf9fe0152..20caf40b4755 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi @@ -220,7 +220,8 @@ qspi1_flash: flash@0 { #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; - spi-max-frequency = <80000000>; + spi-max-frequency = <104000000>; + spi-cs-setup-ns = /bits/ 16 <7>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; m25p,fast-read; -- 2.25.1