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From:   "Limonciello, Mario" <Mario.Limonciello@amd.com>
To:     Hans de Goede <hdegoede@redhat.com>,
        "S-k, Shyam-sundar" <Shyam-sundar.S-k@amd.com>
CC:     "Mahapatra, Rajib" <Rajib.Mahapatra@amd.com>,
        Raul Rangel <rrangel@chromium.org>,
        Mark Gross <markgross@kernel.org>,
        "platform-driver-x86@vger.kernel.org" 
        <platform-driver-x86@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH] platform/x86/amd: pmc: Add a workaround for an s0i3 issue
 on Cezanne
Thread-Topic: [PATCH] platform/x86/amd: pmc: Add a workaround for an s0i3
 issue on Cezanne
Thread-Index: AQHY+dI8jRo8UmESPEy1eO99G5ATd65DJ8GAgAAhWCA=
Date:   Thu, 17 Nov 2022 16:06:59 +0000
Message-ID: <MN0PR12MB6101F972282D66202C95C0F2E2069@MN0PR12MB6101.namprd12.prod.outlook.com>
References: <20221116154341.13382-1-mario.limonciello@amd.com>
 <0d9f8f8c-3b45-dd6a-008b-6d9ffe8ccc93@redhat.com>
In-Reply-To: <0d9f8f8c-3b45-dd6a-008b-6d9ffe8ccc93@redhat.com>
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[Public]


> -----Original Message-----
> From: Hans de Goede <hdegoede@redhat.com>
> Sent: Thursday, November 17, 2022 08:06
> To: Limonciello, Mario <Mario.Limonciello@amd.com>; S-k, Shyam-sundar
> <Shyam-sundar.S-k@amd.com>
> Cc: Mahapatra, Rajib <Rajib.Mahapatra@amd.com>; Raul Rangel
> <rrangel@chromium.org>; Mark Gross <markgross@kernel.org>; platform-
> driver-x86@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] platform/x86/amd: pmc: Add a workaround for an s0i3
> issue on Cezanne
>=20
> Hi Mario,
>=20
> On 11/16/22 16:43, Mario Limonciello wrote:
> > Cezanne platforms under the right circumstances have a synchronization
> > problem where attempting to enter s2idle may fail if the x86 cores are
> > put into HLT before hardware resume from the previous attempt has
> > completed.
> >
> > To avoid this issue add a 10-20ms delay before entering s2idle another
> > time. This workaround will only be applied on interrupts that wake the
> > hardware but don't break the s2idle loop.
> >
> > Cc: "Mahapatra, Rajib" <Rajib.Mahapatra@amd.com>
> > Cc: "Raul Rangel" <rrangel@chromium.org>
> > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
>=20
> Thank you for your patch, I've applied this patch to my review-hans
> branch:
> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgit.k
> ernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fpdx86%2Fplatform-
> drivers-x86.git%2Flog%2F%3Fh%3Dreview-
> hans&amp;data=3D05%7C01%7Cmario.limonciello%40amd.com%7C674f8bf7a8
> 114f83a3b408dac8a4d941%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C
> 0%7C638042907591739047%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLj
> AwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&amp;sdata=3DXYwl%2FOvUFy%2Bgz9EY9oa35M%2BkLf%2Bud8PKXynQ
> FlrUdoE%3D&amp;reserved=3D0
>=20
> Please let me know if it important to get this as a fix into 6.1,
> I wasn't really planning on doing any more fixes pull-reqs for 6.1,
> but I can do one if necessary.
>=20

AFAIK it's a corner case.  I think it can wait until 6.2, but I think it sh=
ould probably
be Cc to 6.1 stable (which has the ability to run code in the check()) phas=
e.

> Once I've run some tests on this branch the patches there will be
> added to the platform-drivers-x86/for-next branch and eventually
> will be included in the pdx86 pull-request to Linus for the next
> merge-window.
>=20
> Regards,
>=20
> Hans
>=20
>=20
> > ---
> >  drivers/platform/x86/amd/pmc.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/platform/x86/amd/pmc.c
> b/drivers/platform/x86/amd/pmc.c
> > index ef4ae977b8e0..439d282aafd1 100644
> > --- a/drivers/platform/x86/amd/pmc.c
> > +++ b/drivers/platform/x86/amd/pmc.c
> > @@ -739,8 +739,14 @@ static void amd_pmc_s2idle_prepare(void)
> >  static void amd_pmc_s2idle_check(void)
> >  {
> >  	struct amd_pmc_dev *pdev =3D &pmc;
> > +	struct smu_metrics table;
> >  	int rc;
> >
> > +	/* CZN: Ensure that future s0i3 entry attempts at least 10ms passed
> */
> > +	if (pdev->cpu_id =3D=3D AMD_CPU_ID_CZN &&
> !get_metrics_table(pdev, &table) &&
> > +	    table.s0i3_last_entry_status)
> > +		usleep_range(10000, 20000);
> > +
> >  	/* Dump the IdleMask before we add to the STB */
> >  	amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
> >