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Date:   Thu, 17 Nov 2022 10:02:20 -0800
From:   Isaku Yamahata <isaku.yamahata@gmail.com>
To:     "Huang, Kai" <kai.huang@intel.com>
Cc:     "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Yamahata, Isaku" <isaku.yamahata@intel.com>,
        "pbonzini@redhat.com" <pbonzini@redhat.com>,
        "Shahar, Sagi" <sagis@google.com>,
        "Aktas, Erdem" <erdemaktas@google.com>,
        "isaku.yamahata@gmail.com" <isaku.yamahata@gmail.com>,
        "dmatlack@google.com" <dmatlack@google.com>,
        "Christopherson,, Sean" <seanjc@google.com>
Subject: Re: [PATCH v10 034/108] KVM: x86/mmu: Add Suppress VE bit to
 shadow_mmio_{value, mask}
Message-ID: <20221117180220.GJ2350331@ls.amr.corp.intel.com>
References: <cover.1667110240.git.isaku.yamahata@intel.com>
 <1c480a48c2697054b1cfe068fa073f4035648f9a.1667110240.git.isaku.yamahata@intel.com>
 <a0d5878b7280372fa2de49156d58f69fa07659cc.camel@intel.com>
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On Wed, Nov 09, 2022 at 11:48:30AM +0000,
"Huang, Kai" <kai.huang@intel.com> wrote:

> On Sat, 2022-10-29 at 23:22 -0700, isaku.yamahata@intel.com wrote:
> > From: Isaku Yamahata <isaku.yamahata@intel.com>
> > 
> > Because TDX will need shadow_mmio_mask to be VMX_SUPPRESS_VE | RWX	
> > shadow_mmio_value to be 0, make VMX EPT case use same value for TDX
> > shadow_mmio_mask.  
> > 
> 
> TDX need to use different mmio_mask/value doesn't mean they need to be changed
> for VMX guest.  I think the true purpose here is to still be able to use a
> global shadow_mmio_mask for both TDX and VMX guests.  So please explicitly call
> out.  

That's right. With this change, per-VM shadow_mmio_{value, mask} can be avoided.
The common value can be used for both VMX and TDX.
-- 
Isaku Yamahata <isaku.yamahata@gmail.com>