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Message-ID: <8cf7f7ae-f2d3-56ad-021e-7cb478032291@linaro.org>
Date:   Fri, 18 Nov 2022 07:02:34 +0000
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Subject: Re: [PATCH 2/2] ASoC: codecs: va-macro: add npl clk
Content-Language: en-US
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        broonie@kernel.org
Cc:     alsa-devel@alsa-project.org, lgirdwood@gmail.com, perex@perex.cz,
        tiwai@suse.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org
References: <20221115105541.16322-1-srinivas.kandagatla@linaro.org>
 <20221115105541.16322-3-srinivas.kandagatla@linaro.org>
 <090831eb-2c7a-56c2-601e-e910431a9403@linaro.org>
From:   Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
In-Reply-To: <090831eb-2c7a-56c2-601e-e910431a9403@linaro.org>
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Precedence: bulk

Thanks Krzysztof,

On 15/11/2022 14:23, Krzysztof Kozlowski wrote:
> On 15/11/2022 11:55, Srinivas Kandagatla wrote:
>> New versions of VA Macro has soundwire integrated, so handle the soundwire npl
>> clock correctly in the codec driver.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
>> ---
>>   sound/soc/codecs/lpass-va-macro.c | 41 +++++++++++++++++++++++++++++++
>>   1 file changed, 41 insertions(+)
>>
>> diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c
>> index b0b6cf29cba3..d59af6d69c34 100644
>> --- a/sound/soc/codecs/lpass-va-macro.c
>> +++ b/sound/soc/codecs/lpass-va-macro.c
>> @@ -205,6 +205,7 @@ struct va_macro {
>>   	int dec_mode[VA_MACRO_NUM_DECIMATORS];
>>   	struct regmap *regmap;
>>   	struct clk *mclk;
>> +	struct clk *npl;
>>   	struct clk *macro;
>>   	struct clk *dcodec;
>>   	struct clk *fsgen;
>> @@ -1332,6 +1333,9 @@ static int fsgen_gate_enable(struct clk_hw *hw)
>>   	struct regmap *regmap = va->regmap;
>>   	int ret;
>>   
>> +	if (va->has_swr_master)
>> +		clk_prepare_enable(va->mclk);
> 
> No error path?
that is true, i missed this indeed, sending v2 with this and other ret = 
PTR_ERR(va->npl) change.

--srini
> 
>> +
>>   	ret = va_macro_mclk_enable(va, true);
>>   	if (!va->has_swr_master)
>>   		return ret;
>> @@ -1358,6 +1362,8 @@ static void fsgen_gate_disable(struct clk_hw *hw)
>>   			   CDC_VA_SWR_CLK_EN_MASK, 0x0);
>>   
>>   	va_macro_mclk_enable(va, false);
>> +	if (va->has_swr_master)
>> +		clk_disable_unprepare(va->mclk);
>>   }
>>   
>>   static int fsgen_gate_is_enabled(struct clk_hw *hw)
>> @@ -1386,6 +1392,9 @@ static int va_macro_register_fsgen_output(struct va_macro *va)
>>   	struct clk_init_data init;
>>   	int ret;
>>   
>> +	if (va->has_swr_master)
>> +		parent = va->npl;
>> +
>>   	parent_clk_name = __clk_get_name(parent);
>>   
>>   	of_property_read_string(np, "clock-output-names", &clk_name);
>> @@ -1512,6 +1521,14 @@ static int va_macro_probe(struct platform_device *pdev)
>>   	/* mclk rate */
>>   	clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
>>   
>> +	if (va->has_swr_master) {
>> +		va->npl = devm_clk_get(dev, "npl");
> 
> I think you miss:
> ret = PTR_ERR(va->npl);
> 
>> +		if (IS_ERR(va->npl))
>> +			goto err;
>> +
>> +		clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ);
>> +	}
>> +
>>   	ret = clk_prepare_enable(va->macro);
>>   	if (ret)
>>   		goto err;
> 
> Best regards,
> Krzysztof
>