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From:   Ulf Hansson <ulf.hansson@linaro.org>
Date:   Fri, 18 Nov 2022 11:06:19 +0100
Message-ID: <CAPDyKFpNMfru+U8r-pnFpyfZ_3_7RdrApdBvcpykV1ccaMMaHQ@mail.gmail.com>
Subject: Re: [PATCH 1/2] mmc: jz4740: Don't change parent clock rate for some SoCs
To:     Siarhei Volkau <lis8215@gmail.com>
Cc:     Paul Cercueil <paul@crapouillou.net>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org
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On Fri, 18 Nov 2022 at 10:52, Siarhei Volkau <lis8215@gmail.com> wrote:
>
> =D0=BF=D1=82, 18 =D0=BD=D0=BE=D1=8F=D0=B1. 2022 =D0=B3. =D0=B2 12:27, Pau=
l Cercueil <paul@crapouillou.net>:
> >
> > Hi,
> >
> > (Ingenic SoCs maintainer here)
> >
> > Le ven. 18 nov. 2022 =C3=A0 09:45:48 +0100, Ulf Hansson
> > <ulf.hansson@linaro.org> a =C3=A9crit :
> > > On Tue, 8 Nov 2022 at 05:53, Siarhei Volkau <lis8215@gmail.com> wrote=
:
> > >>
> > >>  Some SoCs have one clock divider for all MMC units, thus changing
> > >> one
> > >>  affects others as well. This leads to random hangs and memory
> > >>  corruptions, observed on the JZ4755 based device with two MMC slots
> > >>  used at the same time.
> > >
> > > Urgh, that sounds like broken HW to me.
> > >
> > > The MMC blocks could share a parent clock (that would need a fixed
> > > rate for it to be applied), assuming there is a separate gate/divider
> > > available per block. But there isn't'?
> >
> > They do share a parent clock and have separate gates, and each MMC IP
> > block has an internal divider for the bus frequency derived from that
> > shared clock.
> >
> > >>
> > >>  List of SoCs affected includes: JZ4725b, JZ4755, JZ4760 and JZ4760b=
.
> > >>  However, the MMC driver doesn't distinguish JZ4760 and JZ4770
> > >>  which shall remain its behavior. For the JZ4755 is sufficient to
> > >>  use JZ4725b's binding. JZ4750 is outside of the patch.
> > >>
> > >>  The MMC core has its own clock divisor, rather coarse but suitable
> > >> well,
> > >>  and it shall keep the role of tuning clock for the MMC host in that
> > >>  case.
> > >
> > > The mmc core doesn't have a clock divisor, but it does control the bu=
s
> > > clock frequency through the ->set_ios() host ops. It needs to do that=
,
> > > to be able to conform to the (e)MMC, SD and SDIO specifications.
> > >
> > > Can you please try to elaborate on the above, so I can better
> > > understand your point?
> >
> > Yes, I don't really understand the patch, TBH.
> >
> > The "clk_set_rate" call will only set the shared clock to the *maximum*
> > clock frequency (host->mmc->f_max) which should be the exact same
> > across all MMC IPs.
>
> That's the case I need different "f_max" for my HW, for some reason
> internal slot can't do a full rate (48MHz) but the external can, the same
> card used for checking. So I want to set 24M for mmc0, and 48M for mmc1
> with respect to hardware limitation.

This sounds like a board specific problem, right?

The simple solution would be to use 24M for both hosts, but that would
unnecessarily degrade the speed for the host for the internal slot.

It sounds like we need a new DT binding to describe a capped
max-frequency for the "broken slot". And in case that is available in
the DTS, the mmc->f_max value should be overridden with it, while also
respecting the original f_max value while calling clk_set_rate().

Br
Uffe