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Date:   Fri, 18 Nov 2022 16:41:59 +0000
From:   Will Deacon <will@kernel.org>
To:     Jiucheng Xu <jiucheng.xu@amlogic.com>
Cc:     Mark Rutland <mark.rutland@arm.com>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Kevin Hilman <khilman@baylibre.com>,
        Jerome Brunet <jbrunet@baylibre.com>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
        Jianxin Pan <jianxin.pan@amlogic.com>,
        Kelvin Zhang <kelvin.zhang@amlogic.com>,
        Chris Healy <healych@amzon.com>, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-amlogic@lists.infradead.org
Subject: Re: [PATCH v11 1/3] perf/amlogic: Add support for Amlogic meson G12
 SoC DDR PMU driver
Message-ID: <20221118164157.GA4802@willie-the-truck>
References: <20221117083419.2084264-1-jiucheng.xu@amlogic.com>
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On Thu, Nov 17, 2022 at 04:34:15PM +0800, Jiucheng Xu wrote:
> Add support for Amlogic Meson G12 Series SOC - DDR bandwidth PMU driver
> framework and interfaces. The PMU can not only monitor the total DDR
> bandwidth, but also individual IP module bandwidth.
> 
> Signed-off-by: Jiucheng Xu <jiucheng.xu@amlogic.com>
> Tested-by: Chris Healy <healych@amzon.com>

amzon.com?

> +static umode_t meson_ddr_perf_format_attr_visible(struct kobject *kobj,
> +						  struct attribute *attr,
> +						  int n)
> +{
> +	struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj));
> +	struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu);
> +	const u64 *capability = ddr_pmu->info.hw_info->capability;
> +	struct device_attribute *dev_attr;
> +	int id;
> +	char value[20]; // config1:xxx, 20 is enough
> +
> +	dev_attr = container_of(attr, struct device_attribute, attr);
> +	dev_attr->show(NULL, NULL, value);
> +
> +	if (sscanf(value, "config1:%d", &id) == 1)
> +		return capability[0] & (1 << id) ? attr->mode : 0;
> +
> +	if (sscanf(value, "config2:%d", &id) == 1)
> +		return capability[1] & (1 << id) ? attr->mode : 0;

Should these be '(1ULL << id)' to avoid shifting beyond the side of the
32-bit type?

Will