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Fri, 18 Nov 2022 09:39:59 -0800 (PST) X-Received: by 2002:a81:9a0b:0:b0:370:2d3:c361 with SMTP id r11-20020a819a0b000000b0037002d3c361mr7373226ywg.251.1668793199261; Fri, 18 Nov 2022 09:39:59 -0800 (PST) MIME-Version: 1.0 References: <20221118011714.70877-1-hal.feng@starfivetech.com> <20221118011714.70877-7-hal.feng@starfivetech.com> In-Reply-To: From: Emil Renner Berthing Date: Fri, 18 Nov 2022 18:39:43 +0100 Message-ID: Subject: Re: [PATCH v2 6/8] riscv: dts: starfive: Add initial StarFive JH7110 device tree To: Conor Dooley Cc: Hal Feng , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Albert Ou , Ben Dooks , Thomas Gleixner , Marc Zyngier , Stephen Boyd , Michael Turquette , Philipp Zabel , Linus Walleij , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 18 Nov 2022 at 13:01, Conor Dooley wrote: > > On Fri, Nov 18, 2022 at 09:17:12AM +0800, Hal Feng wrote: > > From: Emil Renner Berthing > > > > Add initial device tree for the JH7110 RISC-V SoC by StarFive > > Technology Ltd. > > > > Signed-off-by: Emil Renner Berthing > > Co-developed-by: Jianlong Huang > > Signed-off-by: Jianlong Huang > > Co-developed-by: Hal Feng > > Signed-off-by: Hal Feng > > --- > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 437 +++++++++++++++++++++++ > > 1 file changed, 437 insertions(+) > > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > new file mode 100644 > > index 000000000000..c22e8f1d2640 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi > > @@ -0,0 +1,437 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR MIT > > +/* > > + * Copyright (C) 2022 StarFive Technology Co., Ltd. > > + * Copyright (C) 2022 Emil Renner Berthing > > @Emil, I feel like I have to ask given the 2022 date, but should this > stuff be attributed to your canonical address or is this fine? Yeah, this is fine. I did this on my own time before I was actually tasked with working on the JH7110 based boards. > Other than that, a cursory check /looks/ fine, other than the: > > > + gmac0_rgmii_rxin: gmac0_rgmii_rxin { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + /* This value must be overridden by the board */ > > + clock-frequency = <0>; > > + }; > > If you remove the clock-frequency = <0> bit, dtb validation will force > people to set the value in jh7110-board.dts which I'd prefer to rely on > than a comment. > > Glad to see you sorted out the clock/reset stuff too! > > Thanks, > Conor. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > >