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Date:   Fri, 18 Nov 2022 22:38:56 +0100
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Subject: Re: [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache
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From:   Peter Rosin <peda@axentia.se>
To:     linux-kernel@vger.kernel.org
Cc:     Russell King <linux@armlinux.org.uk>,
        Nicolas Ferre <nicolas.ferre@microchip.com>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
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        =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <clement.leger@bootlin.com>,
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Hi!

2022-11-12 at 16:40, Peter Rosin wrote:
> The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but
> apparently not for the older SAMA5D3. At least not always.
> 
> Solves a build-time regression with the following symptom:
> 
> sama5.c:(.init.text+0x48): undefined reference to `outer_cache'
> 
> Fixes: 3b5a7ca7d252 ("ARM: at91: setup outer cache .write_sec() callback if needed")
> Signed-off-by: Peter Rosin <peda@axentia.se>
> ---
>  arch/arm/mach-at91/sama5.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Hi!
> 
> I'm not sure this is the correct solution? Maybe SAMA5D3 should bring
> in CONFIG_OUTER_CACHE unconditionally instead? But that seems like a
> bigger change, and not just a tweak of the regressing commit...
> 
> Cheers,
> Peter
> 
> diff --git a/arch/arm/mach-at91/sama5.c b/arch/arm/mach-at91/sama5.c
> index 67ed68fbe3a5..bf2b5c6a18c6 100644
> --- a/arch/arm/mach-at91/sama5.c
> +++ b/arch/arm/mach-at91/sama5.c
> @@ -26,7 +26,7 @@ static void sama5_l2c310_write_sec(unsigned long val, unsigned reg)
>  static void __init sama5_secure_cache_init(void)
>  {
>  	sam_secure_init();
> -	if (sam_linux_is_optee_available())
> +	if (IS_ENABLED(CONFIG_OUTER_CACHE) && sam_linux_is_optee_available())
>  		outer_cache.write_sec = sama5_l2c310_write_sec;
>  }
>  

It's been a week or so of silence, thus CC:ing the regression bot so
that this issue is not lost.

Cheers,
Peter

#regzbot ^introduced: 3b5a7ca7d252 
#regzbot title: Build-time failure for SAMA5D3