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Date:   Sat, 19 Nov 2022 11:10:42 +0800
From:   Shawn Guo <shawnguo@kernel.org>
To:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc:     s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
        linux-imx@nxp.com, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, Peng Fan <peng.fan@nxp.com>,
        Marco Felsch <m.felsch@pengutronix.de>
Subject: Re: [PATCH V6 10/12] arm64: dts: imx8mn-evk: enable uart1
Message-ID: <20221119031039.GK16229@T480>
References: <20221117095403.1876071-1-peng.fan@oss.nxp.com>
 <20221117095403.1876071-11-peng.fan@oss.nxp.com>
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On Thu, Nov 17, 2022 at 05:54:01PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
> 
> Enable uart1 for BT usage
> Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
> could only support max 1.5M buadrate if using OSC_24M as clock source.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
> ---
>  arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> index 2439b91e51d8..dfa11927b1d7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
> @@ -247,6 +247,15 @@ &spdif1 {
>  	status = "okay";
>  };
>  
> +&uart1 { /* BT */
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	assigned-clocks = <&clk IMX8MN_CLK_UART1>;
> +	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
> +	fsl,uart-has-rtscts;

uart-has-rtscts

Fixed it up and applied, thanks!

Shawn

> +	status = "okay";
> +};
> +
>  &uart2 { /* console */
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pinctrl_uart2>;
> @@ -444,6 +453,15 @@ MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
>  		>;
>  	};
>  
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
> +			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
> +			MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
> +			MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
> +		>;
> +	};
> +
>  	pinctrl_uart2: uart2grp {
>  		fsl,pins = <
>  			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
> -- 
> 2.37.1
>