Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Date:   Sat, 19 Nov 2022 07:07:41 -0700
From:   Alex Williamson <alex.williamson@redhat.com>
To:     Christian =?UTF-8?B?S8O2bmln?= <christian.koenig@amd.com>
Cc:     "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        linux-kernel@vger.kernel.org
Subject: Re: [RFC] Resizable BARs vs bridges with BARs
Message-ID: <20221119070741.7038464f.alex.williamson@redhat.com>
In-Reply-To: <fe0e40cb-b982-2aba-b622-8534c174ea39@amd.com>
References: <20221118160916.7e165306.alex.williamson@redhat.com>
        <fe0e40cb-b982-2aba-b622-8534c174ea39@amd.com>
Organization: Red Hat
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
Precedence: bulk

Hi Christian,

On Sat, 19 Nov 2022 12:02:55 +0100
Christian K=C3=B6nig <christian.koenig@amd.com> wrote:

> Hi Alex,
>=20
> Am 19.11.22 um 00:09 schrieb Alex Williamson:
> > Hi,
> >
> > I'm trying to get resizable BARs working in a configuration where my
> > root bus resources provide plenty of aperture for the BAR:
> >
> > pci_bus 0000:5d: root bus resource [io  0x8000-0x9fff window]
> > pci_bus 0000:5d: root bus resource [mem 0xb8800000-0xc5ffffff window]
> > pci_bus 0000:5d: root bus resource [mem 0xb000000000-0xbfffffffff windo=
w] <<<
> > pci_bus 0000:5d: root bus resource [bus 5d-7f]
> >
> > But resizing fails with -ENOSPC.  The topology looks like this:
> >
> >   +-[0000:5d]-+-00.0-[5e-61]----00.0-[5f-61]--+-01.0-[60]----00.0  Inte=
l Corporation DG2 [Arc A380]
> >                                               \-04.0-[61]----00.0  Inte=
l Corporation Device 4f92
> >
> > The BIOS is not fluent in resizable BARs and only programs the root
> > port with a small aperture:
> >
> > 5d:00.0 PCI bridge: Intel Corporation Sky Lake-E PCI Express Root Port =
A (rev 07) (prog-if 00 [Normal decode])
> >          Bus: primary=3D5d, secondary=3D5e, subordinate=3D61, sec-laten=
cy=3D0
> >          I/O behind bridge: 0000f000-00000fff [disabled]
> >          Memory behind bridge: b9000000-ba0fffff [size=3D17M]
> >          Prefetchable memory behind bridge: 000000bfe0000000-000000bff0=
7fffff [size=3D264M]
> >          Kernel driver in use: pcieport
> >
> > The trouble comes on the upstream PCIe switch port:
> >
> > 5e:00.0 PCI bridge: Intel Corporation Device 4fa1 (rev 01) (prog-if 00 =
[Normal decode]) =20
> >     >>>  Region 0: Memory at b010000000 (64-bit, prefetchable) =20
> >          Bus: primary=3D5e, secondary=3D5f, subordinate=3D61, sec-laten=
cy=3D0
> >          I/O behind bridge: 0000f000-00000fff [disabled]
> >          Memory behind bridge: b9000000-ba0fffff [size=3D17M]
> >          Prefetchable memory behind bridge: 000000bfe0000000-000000bfef=
ffffff [size=3D256M]
> >          Kernel driver in use: pcieport
> >
> > Note region 0 of this bridge, which is 64-bit, prefetchable and
> > therefore conflicts with the same type for the resizable BAR on the GPU:
> >
> > 60:00.0 VGA compatible controller: Intel Corporation DG2 [Arc A380] (re=
v 05) (prog-if 00 [VGA controller])
> >          Region 0: Memory at b9000000 (64-bit, non-prefetchable) [disab=
led] [size=3D16M]
> >          Region 2: Memory at bfe0000000 (64-bit, prefetchable) [disable=
d] [size=3D256M]
> >          Expansion ROM at <ignored> [disabled]
> >          Capabilities: [420 v1] Physical Resizable BAR
> >                  BAR 2: current size: 256MB, supported: 256MB 512MB 1GB=
 2GB 4GB 8GB
> >
> > It's a shame that the hardware designers didn't mark the upstream port
> > BAR as non-prefetchable to avoid it living in the same resource
> > aperture as the resizable BAR on the downstream device. =20
>=20
> This is expected. Bridges always have a 32bit non prefetchable and a=20
> 64bit prefetchable BAR. This is part of the PCI(e) spec.

To be clear, the issue is a bridge implementing a 64-bit, prefetchable
BAR at config offset 0x10 & 0x14, not the limit/base registers that
define the bridge windows for prefetchable and non-prefetchable
downstream resources.

> > In any case, it's my understanding that our bridge drivers don't genera=
lly make use
> > of bridge BARs.  I think we can test whether a driver has done a
> > pci_request_region() or equivalent by looking for the IORESOURCE_BUSY
> > flag, but I also suspect this is potentially racy. =20
>=20
> That sounds like we have a misunderstanding here how those bridges work.=
=20
> The upstream bridges should include all the resources of the downstream=20
> devices/bridges in their BARs.

Correct, and the issue is that the bridge at 5e:00.0 _consumes_ a
portion of the window we need to resize at the root port.

Root port:
Prefetchable memory behind bridge: 000000bfe0000000-000000bff07fffff [size=
=3D264M]

Upstream switch port:
Region 0: Memory at b010000000 (64-bit, prefetchable)
Prefetchable memory behind bridge: 000000bfe0000000-000000bfefffffff [size=
=3D256M]

It's that Region 0 resource that prevents resizing.

> > The patch below works for me, allowing the new resourceN_resize sysfs
> > attribute to resize the root port window within the provided bus
> > window.  Is this the right answer?  How can we make it feel less
> > sketchy?  Thanks, =20
>=20
> The correct approach is to remove all the drivers (EFI, vesafb etc...)=20
> which are using the PCI(e) devices under the bridge in question. Then=20
> release the resources and puzzle everything back together.
>=20
> See amdgpu_device_resize_fb_bar() how to do this correctly.

Resource resizing in pci-sysfs is largely modeled after the amdgpu
code, but I don't see any special provisions for handling conflicting
resources consumed on intermediate devices.  The driver attached to the
upstream switch port is pcieport and removing it doesn't resolve the
problem.  The necessary resource on the root port still reports a
child.

Is amdgppu resizing known to work in cases where the GPU is downstream
of a PCIe switch that consumes resources of the same type and the root
port aperture needs to be resized?  I suspect it does not.  Thanks,

Alex