Received: by 2002:a05:6358:d09b:b0:dc:cd0c:909e with SMTP id jc27csp2874857rwb; Sun, 20 Nov 2022 03:23:02 -0800 (PST) X-Google-Smtp-Source: AA0mqf5CtNgOnI4eCn6S7BLVBk2Huae2+LAj5x4tM9sWTBl/dTy97tv9ruGAApBpiZkh0zC/4rsu X-Received: by 2002:a17:906:35c8:b0:78d:3a04:e41d with SMTP id p8-20020a17090635c800b0078d3a04e41dmr12256771ejb.39.1668943382488; Sun, 20 Nov 2022 03:23:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668943382; cv=none; d=google.com; s=arc-20160816; b=1HDJyqFbmSJwc3e4uV9ejtdwXkGM7zMOrNHWHKezC6sV1X0/DcaAfXxHO/5TLHfc0Z nLN4IQNOtexbTCeasFp+0FB+9lilon1O8pzSvUcH3u3z+hokKo63tHL+yjJz1IYjFJR8 RbTzH/r5MdER7lGt0eEuwaCiY4ogVoFZGhBEnlXIcHYzI4WSy7H8spG1z9hWsX3qPqj2 V/hPjz/x+TNLc3RumtFWX9OUyN3k/5tYcEs69WP8QHjwlo70a8LgvivBk7LIAOxwTIiP uU6JgkaTViceIEIQA9rof2ShO/g4KCxbjyZhGlfp3Mt6IpX+sTuywWU4h8aX2ghq6tFo zj1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:in-reply-to:from :references:cc:to:content-language:subject:user-agent:mime-version :date:message-id:dkim-signature; bh=xIr2q8Y2l+wilwdG0V6wIg0brdQLEMLT5ARBL9F/arc=; b=oqOxyar0Qzw4AbL+tnB90u8lN7iGTARjwdkryileG01yXcfsYJm5qt7CUV63gt6BEl Mze7vTjTzEpHhWKdKQKHU0v21IDdkfKAuZ19ssjI7JIPQHchE3OYCRNYSsTlo3czMNA+ ehs6uwZ/LmwN3G56P9m9nyjHEi53c/4G4Q5j86t/9gSMSD/jRhZeHmnfGatGPquUafRQ yEPozGTI/4dbIG6dHEDbGK2wA4XIkLI2PzS6YIy71K/8aUam63+09bB9T3N5JkYlHOw3 Z4BFfCKPiJ35fgViBEE0qQQ6/nvf7Vk3NwUSKh5hlwg8oMqOSCd7x3o+A4fhnX1k7VSn 27Eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s9Qk4HhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y18-20020a056402441200b00458ac23f0b8si7684380eda.399.2022.11.20.03.22.39; Sun, 20 Nov 2022 03:23:02 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s9Qk4HhV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229739AbiKTLHC (ORCPT + 92 others); Sun, 20 Nov 2022 06:07:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229558AbiKTLHA (ORCPT ); Sun, 20 Nov 2022 06:07:00 -0500 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64DBD920BC for ; Sun, 20 Nov 2022 03:06:59 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id z24so11732023ljn.4 for ; Sun, 20 Nov 2022 03:06:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=xIr2q8Y2l+wilwdG0V6wIg0brdQLEMLT5ARBL9F/arc=; b=s9Qk4HhV4hMqLWoMFAqH4DkqhT7EWeeGt8eAonfz3fDKDAEAe7KjNF8GzBmZWtptKX 3AkHh52nyS3Ui6E139WNcvaQC628YYRJZK5H2Dbe2LWM9ZN6SGmGIQV/RxBUgQ24i5dh MbFndQV9XMgtMaXLQMFPgCvlNwofOuheQGUECN+7sAGkmcevaf3Wyeucn/Ze1EqhOr6x ExI5DjPrw1imJSwGyy63qdIvqsRX5Xyi8HN7c9BQ1qYc7WaYlAi0STLprYtyc00BYBPs uyMDSvchCzrK0FQiytuvn+mOLwzIoPcmt7zgne7OBfJ8WWziK39wdbB2t80V3AGrYaGO q+3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xIr2q8Y2l+wilwdG0V6wIg0brdQLEMLT5ARBL9F/arc=; b=hoWKqWIJNr+xDGSJ4ccrTSzHI8cPZhV96BcjQZ37KuSZcxLUOk49hXH89zuUtSFzWj z3lXM8Bl9LoVOE2t1I3x0+mhcRbHv10u6J/xUhn7hmAV17+Sd5E83drjK5BDD8tslYAx gf7ydmEG9lE9lVr/BEqcfVnXy/dkVw3l/da+TBd7V++2GEnfaAAjRw7ixK7T4ExFYjY/ l3lWG/Rr5/Ps6po2T/fqNbjrs5YvfnQf0i4PYu3zGI8NZrqgRIp069uiELNe9JkkDrSe xXWJqBKQT8RCKLpKDDUZY8PhgQz+1a+NnexPpQhKz+7Im8e4olDxmtXpMKo9/lipgVHp voSw== X-Gm-Message-State: ANoB5pm6q3jFXyAoxYBuHMwYRQaQ+0CL1vMkDRIlij8veg1BWRrJfZqG wGRE2RoNzVygy/l+p5nadPnmxQ== X-Received: by 2002:a2e:990b:0:b0:277:5a8:91c8 with SMTP id v11-20020a2e990b000000b0027705a891c8mr4137786lji.173.1668942417657; Sun, 20 Nov 2022 03:06:57 -0800 (PST) Received: from [192.168.0.20] (088156142067.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.67]) by smtp.gmail.com with ESMTPSA id q29-20020ac25a1d000000b00497aa190523sm1511887lfn.248.2022.11.20.03.06.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Nov 2022 03:06:56 -0800 (PST) Message-ID: Date: Sun, 20 Nov 2022 12:06:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 1/2] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocks Content-Language: en-US To: Melody Olvera , Andy Gross , Bjorn Andersson , Michael Turquette , Konrad Dybcio , Stephen Boyd , Rob Herring , Krzysztof Kozlowski Cc: Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221118181826.28269-1-quic_molvera@quicinc.com> <20221118181826.28269-2-quic_molvera@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <20221118181826.28269-2-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/11/2022 19:18, Melody Olvera wrote: > Add device tree bindings for global clock controller on QDU1000 and > QRU1000 SoCs. > > Signed-off-by: Melody Olvera > --- > .../bindings/clock/qcom,gcc-qdu1000.yaml | 70 ++++++++ > include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++++++++++++++++++ > 2 files changed, 240 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > new file mode 100644 > index 000000000000..90935a6795ee > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdu1000.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +maintainers: > + - Melody Olvera > + > +description: | > + Qualcomm global clock control module which supports the clocks, resets and > + power domains on QDU1000 and QRU1000 Keep the same style as existing files. They were cleaned up recently. > + > + See also: > + - include/dt-bindings/clock/qcom,gcc-qdu1000.h Keep the same style, so missing '::', drop '- '. > + > +properties: > + compatible: > + items: > + - const: qcom,gcc-qdu1000 SM8550 is coming with proper style of compatible, so let's do the same also here: qcom,qdu1000-gcc (and file name matching it) > + - const: syscon I don't see usage of it as syscon. Which parts of GCC are needed for whom? > + > + clocks: > + items: > + - description: Board XO source > + - description: Sleep clock source > + - description: PCIE 0 Pipe clock source > + - description: PCIE 0 Phy Auxiliary clock source > + - description: USB3 Phy wrapper pipe clock source > + minItems: 2 Same question as for SM8550 - why inputs are flexible? Either you have these or you do not. > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 Missing ref to gcc.yaml. Drop all properties provided by gcc.yaml. > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - '#clock-cells' > + - '#reset-cells' Drop these required by gcc.yaml. Best regards, Krzysztof