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[95.49.32.48]) by smtp.gmail.com with ESMTPSA id y22-20020a196416000000b004a25bb4494fsm1996610lfb.178.2022.11.21.03.03.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Nov 2022 03:03:52 -0800 (PST) Message-ID: <8341830c-a09c-9366-096a-d58d34da36bd@linaro.org> Date: Mon, 21 Nov 2022 12:03:50 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [PATCH v4 1/2] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs To: Melody Olvera , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221118192241.29384-1-quic_molvera@quicinc.com> <20221118192241.29384-2-quic_molvera@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20221118192241.29384-2-quic_molvera@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18.11.2022 20:22, Melody Olvera wrote: > Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base > descriptions of CPUs, GCC, RPMHCC, QUP, TLMM, and interrupt-controller > to boot to shell with console on these SoCs. > > Signed-off-by: Melody Olvera > --- > arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1406 +++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/qru1000.dtsi | 27 + > 2 files changed, 1433 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi > create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > new file mode 100644 > index 000000000000..8f1b52cc8ff4 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi > @@ -0,0 +1,1406 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include Hi! Please sort these. > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen: chosen { }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + power-domain-names = "psci"; > + power-domains = <&CPU_PD0>; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + power-domains = <&CPU_PD1>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_100>; > + L2_100: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + power-domains = <&CPU_PD2>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_200>; > + L2_200: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + power-domains = <&CPU_PD3>; > + power-domain-names = "psci"; > + qcom,freq-domains = <&cpufreq_hw 0>; > + next-level-cache = <&L2_300>; > + L2_300: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + }; > + }; > + > + idle-states { > + entry-method = "psci"; > + > + CPU_OFF: cpu-sleep-0 { > + compatible = "arm,idle-state"; > + entry-latency-us = <274>; > + exit-latency-us = <480>; > + min-residency-us = <3934>; > + arm,psci-suspend-param = <0x40000004>; > + local-timer-stop; > + }; > + }; > + > + domain-idle-states { > + CLUSTER_SLEEP_0: cluster-sleep-0 { > + compatible = "domain-idle-state"; > + entry-latency-us = <584>; > + exit-latency-us = <2332>; > + min-residency-us = <6118>; > + arm,psci-suspend-param = <0x41000044>; > + }; > + > + CLUSTER_SLEEP_1: cluster-sleep-1 { > + compatible = "domain-idle-state"; > + entry-latency-us = <2893>; > + exit-latency-us = <4023>; > + min-residency-us = <9987>; > + arm,psci-suspend-param = <0x41003344>; > + }; > + }; > + > + firmware { > + scm { > + compatible = "qcom,scm-qdu1000", "qcom,scm"; > + }; > + }; > + > + mc_virt: interconnect-0 { > + compatible = "qcom,qdu1000-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + clk_virt: interconnect-1 { > + compatible = "qcom,qdu1000-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + pmu { > + compatible = "arm,armv8-pmuv3"; > + interrupts = ; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + > + CPU_PD0: power-domain-cpu0 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD1: power-domain-cpu1 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD2: power-domain-cpu2 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CPU_PD3: power-domain-cpu3 { > + #power-domain-cells = <0>; > + power-domains = <&CLUSTER_PD>; > + domain-idle-states = <&CPU_OFF>; > + }; > + > + CLUSTER_PD: power-domain-cluster { > + #power-domain-cells = <0>; > + domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>; > + }; > + }; > + > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + hyp_mem: memory@80000000 { Nodes should not use 'memory@', but something more descriptive, in this case you can use hyp@, for example. > + no-map; > + reg = <0x0 0x80000000 0x0 0x600000>; Please make reg the first property. > + }; > + > + xbl_dt_log_mem: memory@80600000 { > + no-map; > + reg = <0x0 0x80600000 0x0 0x40000>; > + }; > + > + xbl_ramdump_mem: memory@80640000 { > + no-map; > + reg = <0x0 0x80640000 0x0 0x1c0000>; > + }; > + > + aop_image_mem: memory@80800000 { > + no-map; > + reg = <0x0 0x80800000 0x0 0x60000>; > + }; > + > + aop_cmd_db_mem: memory@80860000 { > + compatible = "qcom,cmd-db"; > + no-map; > + reg = <0x0 0x80860000 0x0 0x20000>; > + }; > + > + aop_config_mem: memory@80880000 { > + no-map; > + reg = <0x0 0x80880000 0x0 0x20000>; > + }; > + > + tme_crash_dump_mem: memory@808a0000 { > + no-map; > + reg = <0x0 0x808a0000 0x0 0x40000>; > + }; > + > + tme_log_mem: memory@808e0000 { > + no-map; > + reg = <0x0 0x808e0000 0x0 0x4000>; > + }; > + > + uefi_log_mem: memory@808e4000 { > + no-map; > + reg = <0x0 0x808e4000 0x0 0x10000>; > + }; > + > + /* secdata region can be reused by apps */ > + > + smem_mem: memory@80900000 { > + compatible = "qcom,smem"; > + no-map; > + reg = <0x0 0x80900000 0x0 0x200000>; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: memory@80b00000 { > + no-map; > + reg = <0x0 0x80b00000 0x0 0x100000>; > + }; > + > + xbl_sc_mem: memory@80c00000 { > + no-map; > + reg = <0x0 0x80c00000 0x0 0x40000>; > + }; > + > + /* uefi region can be reused by apps */ > + > + tz_stat_mem: memory@81d00000 { > + no-map; > + reg = <0x0 0x81d00000 0x0 0x100000>; > + }; > + > + tags_mem: memory@81e00000 { > + no-map; > + reg = <0x0 0x81e00000 0x0 0x500000>; > + }; > + > + qtee_mem: memory@82300000 { > + no-map; > + reg = <0x0 0x82300000 0x0 0x500000>; > + }; > + > + ta_mem: memory@82800000 { > + no-map; > + reg = <0x0 0x82800000 0x0 0xa00000>; > + }; > + > + fs1_mem: memory@83200000 { > + no-map; > + reg = <0x0 0x83200000 0x0 0x400000>; > + }; > + > + fs2_mem: memory@83600000 { > + no-map; > + reg = <0x0 0x83600000 0x0 0x400000>; > + }; > + > + fs3_mem: memory@83a00000 { > + no-map; > + reg = <0x0 0x83a00000 0x0 0x400000>; > + }; > + > + /* Linux kernel image is loaded at 0x83e00000 */ > + > + ipa_fw_mem: memory@8be00000 { > + no-map; > + reg = <0x0 0x8be00000 0x0 0x10000>; > + }; > + > + ipa_gsi_mem: memory@8be10000 { > + no-map; > + reg = <0x0 0x8be10000 0x0 0x14000>; > + }; > + > + mpss_mem: memory@8c000000 { > + no-map; > + reg = <0x0 0x8c000000 0x0 0x12c00000>; > + }; > + > + q6_mpss_dtb_mem: memory@9ec00000 { > + no-map; > + reg = <0x0 0x9ec00000 0x0 0x80000>; > + }; > + > + tenx_mem: memory@a0000000 { > + no-map; > + reg = <0x0 0xa0000000 0x0 0x19600000>; > + }; > + > + oem_tenx_mem: memory@b9600000 { > + no-map; > + reg = <0x0 0xb9600000 0x0 0x6a00000>; > + }; > + > + tenx_q6_buffer_mem: memory@c0000000 { > + no-map; > + reg = <0x0 0xc0000000 0x0 0x3200000>; > + }; > + > + ipa_buffer_mem: memory@c3200000 { > + no-map; > + reg = <0x0 0xc3200000 0x0 0x12c00000>; > + }; > + }; > + > + soc: soc@0 { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + dma-ranges = <0 0 0 0 0x10 0>; > + compatible = "simple-bus"; > + > + gcc: clock-controller@80000 { > + compatible = "qcom,gcc-qdu1000", "syscon"; > + reg = <0x0 0x80000 0x0 0x1f4200>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; Please move #-cells below clocks. > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, > + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, > + <&usb3_phy_wrapper_pipe_clk>; > + }; > + > + gpi_dma0: dma-controller@900000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; > + #dma-cells = <3>; > + reg = <0x0 0x900000 0x0 0x60000>; compatible and reg should go first. > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0xf6 0x0>; > + }; > + > + qupv3_id_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0x9c0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > + iommus = <&apps_smmu 0xe3 0x0>; > + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 > + &clk_virt SLAVE_QUP_CORE_0 0>; > + interconnect-names = "qup-core"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + status = "disabled"; > + > + uart0: serial@980000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x980000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart0_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c1: i2c@984000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x984000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c1_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi1: spi@984000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x984000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; > + status = "disabled"; > + }; > + > + i2c2: i2c@988000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x988000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c2_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi2: spi@988000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x988000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; > + status = "disabled"; > + }; > + > + i2c3: i2c@98c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c3_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi3: spi@98c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x98c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; > + status = "disabled"; > + }; > + > + i2c4: i2c@990000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x990000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c4_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi4: spi@990000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x990000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; > + status = "disabled"; > + }; > + > + i2c5: i2c@994000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x994000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c5_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi5: spi@994000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x994000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; > + status = "disabled"; > + }; > + > + i2c6: i2c@998000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0x998000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c6_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi6: spi@998000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0x998000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; > + status = "disabled"; > + }; > + > + uart7: serial@99c000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0x0 0x99c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + }; > + > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; > + #dma-cells = <3>; > + reg = <0x0 0xa00000 0x0 0x60000>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <12>; > + dma-channel-mask = <0x3f>; > + iommus = <&apps_smmu 0x116 0x0>; > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0xac0000 0x0 0x2000>; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + clock-names = "m-ahb", "s-ahb"; > + iommus = <&apps_smmu 0x103 0x0>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + ranges; > + status = "disabled"; > + > + uart8: serial@a80000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa80000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart8_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + i2c9: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c9_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi9: spi@a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa84000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; > + status = "disabled"; > + }; > + > + i2c10: i2c@a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c10_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi10: spi@a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa88000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; > + status = "disabled"; > + }; > + > + i2c11: i2c@a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c11_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi11: spi@a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; > + status = "disabled"; > + }; > + > + i2c12: i2c@a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c12_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi12: spi@a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa90000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; > + status = "disabled"; > + }; > + > + i2c13: i2c@a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c13_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + uart13: serial@a94000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_uart13_default>; > + interrupts = ; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi13: spi@a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa94000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; > + status = "disabled"; > + }; > + > + i2c14: i2c@a98000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + interrupts = ; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_i2c14_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi14: spi@a98000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa98000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; > + status = "disabled"; > + }; > + > + i2c15: i2c@a9c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + interrupts = ; > + pinctrl-0 = <&qup_i2c15_data_clk>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; > + > + spi15: spi@a9c000 { > + compatible = "qcom,geni-spi"; > + reg = <0x0 0xa9c000 0x0 0x4000>; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = ; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + pinctrl-names = "default"; > + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; > + status = "disabled"; > + }; > + }; > + > + system_noc: interconnect@1640000 { > + reg = <0x0 0x1640000 0x0 0x45080>; > + compatible = "qcom,qdu1000-system-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x1f40000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,qdu1000-pdc", "qcom,pdc"; > + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; > + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, > + <94 609 31>, <125 63 1>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0x0 0xc400000 0x0 0x3000>, > + <0x0 0xc500000 0x0 0x400000>, > + <0x0 0xc440000 0x0 0x80000>, > + <0x0 0xc4c0000 0x0 0x10000>, > + <0x0 0xc42d000 0x0 0x4000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,qdu1000-tlmm"; > + reg = <0x0 0xf000000 0x0 0x1000000>; > + interrupts = ; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 151>; > + wakeup-parent = <&pdc>; > + > + qup_uart0_default: qup-uart0-default-state { > + pins = "gpio6", "gpio7", "gpio8", "gpio9"; > + function = "qup00"; > + }; > + > + qup_i2c1_data_clk: qup-i2c1-data-clk-state { > + pins = "gpio10", "gpio11"; > + function = "qup01"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi1_data_clk: qup-spi1-data-clk-state { > + pins = "gpio10", "gpio11", "gpio12"; > + function = "qup01"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi1_cs: qup-spi1-cs-state { > + pins = "gpio13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c2_data_clk: qup-i2c2-data-clk-state { > + pins = "gpio12", "gpio13"; > + function = "qup02"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi2_data_clk: qup-spi2-data-clk-state { > + pins = "gpio12", "gpio13", "gpio10"; > + function = "qup02"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi2_cs: qup-spi2-cs-state { > + pins = "gpio11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c3_data_clk: qup-i2c3-data-clk-state { > + pins = "gpio14", "gpio15"; > + function = "qup03"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi3_data_clk: qup-spi3-data-clk-state { > + pins = "gpio14", "gpio15", "gpio16"; > + function = "qup03"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi3_cs: qup-spi3-cs-state { > + pins = "gpio17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c4_data_clk: qup-i2c4-data-clk-state { > + pins = "gpio16", "gpio17"; > + function = "qup04"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi4_data_clk: qup-spi4-data-clk-state { > + pins = "gpio16", "gpio17", "gpio14"; > + function = "qup04"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi4_cs: qup-spi4-cs-state { > + pins = "gpio15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c5_data_clk: qup-i2c5-data-clk-state { > + pins = "gpio130", "gpio131"; > + function = "qup05"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi5_data_clk: qup-spi5-data-clk-state { > + pins = "gpio130", "gpio131", "gpio132"; > + function = "qup05"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi5_cs: qup-spi5-cs-state { > + pins = "gpio133"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c6_data_clk: qup-i2c6-data-clk-state { > + pins = "gpio132", "gpio133"; > + function = "qup06"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi6_data_clk: qup-spi6-data-clk-state { > + pins = "gpio132", "gpio133", "gpio130"; > + function = "qup06"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi6_cs: qup-spi6-cs-state { > + pins = "gpio131"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart7_rx: qup-uart7-rx-state { > + pins = "gpio135"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart7_tx: qup-uart7-tx-state { > + pins = "gpio134"; > + function = "qup07"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + qup_uart8_default: qup-uart8-default-state { > + pins = "gpio18", "gpio19", "gpio20", "gpio21"; > + function = "qup10"; > + }; > + > + qup_i2c9_data_clk: qup-i2c9-data-clk-state { > + pins = "gpio22", "gpio23"; > + function = "qup11"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi9_data_clk: qup-spi9-data-clk-state { > + pins = "gpio22", "gpio23", "gpio24"; > + function = "qup11"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi9_cs: qup-spi9-cs-state { > + pins = "gpio25"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c10_data_clk: qup-i2c10-data-clk-state { > + pins = "gpio24", "gpio25"; > + function = "qup12"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi10_data_clk: qup-spi10-data-clk-state { > + pins = "gpio24", "gpio25", "gpio22"; > + function = "qup12"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi10_cs: qup-spi10-cs-state { > + pins = "gpio23"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c11_data_clk: qup-i2c11-data-clk-state { > + pins = "gpio26", "gpio27"; > + function = "qup13"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi11_data_clk: qup-spi11-data-clk-state { > + pins = "gpio26", "gpio27", "gpio28"; > + function = "qup13"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi11_cs: qup-spi11-cs-state { > + pins = "gpio29"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c12_data_clk: qup-i2c12-data-clk-state { > + pins = "gpio28", "gpio29"; > + function = "qup14"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi12_data_clk: qup-spi12-data-clk-state { > + pins = "gpio28", "gpio29", "gpio26"; > + function = "qup14"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi12_cs: qup-spi12-cs-state { > + pins = "gpio27"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c13_data_clk: qup-i2c13-data-clk-state { > + pins = "gpio30", "gpio31"; > + function = "qup15"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi13_data_clk: qup-spi13-data-clk-state { > + pins = "gpio30", "gpio31", "gpio32"; > + function = "qup15"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi13_cs: qup-spi13-cs-state { > + pins = "gpio33"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_uart13_default: qup-uart13-default-state { > + pins = "gpio30", "gpio31", "gpio32", "gpio33"; > + function = "qup15"; > + }; > + > + qup_i2c14_data_clk: qup-i2c14-data-clk-state { > + pins = "gpio34", "gpio35"; > + function = "qup16"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi14_data_clk: qup-spi14-data-clk-state { > + pins = "gpio34", "gpio35", "gpio36"; > + function = "qup16"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi14_cs: qup-spi14-cs-state { > + pins = "gpio37", "gpio38"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_i2c15_data_clk: qup-i2c15-data-clk-state { > + pins = "gpio40", "gpio41"; > + function = "qup17"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi15_data_clk: qup-spi15-data-clk-state { > + pins = "gpio40", "gpio41", "gpio30"; > + function = "qup17"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi15_cs: qup-spi15-cs-state { > + pins = "gpio31"; > + drive-strength = <6>; > + bias-disable; > + }; > + }; > + > + apps_smmu: iommu@15000000 { > + compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + }; > + > + intc: interrupt-controller@17200000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ > + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ compatible and reg should go first. > + interrupts = ; > + }; > + > + timer@17420000 { > + compatible = "arm,armv7-timer-mem"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + reg = <0x0 0x17420000 0x0 0x1000>; compatible and reg should go first. > + clock-frequency = <19200000>; This should be removed if not necessary (on qcom CNTFRQ_ELn is configured earlier, anyway). > + > + frame@17421000 { > + frame-number = <0>; > + interrupts = , > + ; > + reg = <0x17421000 0x1000>, > + <0x17422000 0x1000>; Please move reg up, in all subnodes. > + }; > + > + frame@17423000 { > + frame-number = <1>; > + interrupts = ; > + reg = <0x17423000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17425000 { > + frame-number = <2>; > + interrupts = ; > + reg = <0x17425000 0x1000>, > + <0x17426000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17427000 { > + frame-number = <3>; > + interrupts = ; > + reg = <0x17427000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17429000 { > + frame-number = <4>; > + interrupts = ; > + reg = <0x17429000 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742b000 { > + frame-number = <5>; > + interrupts = ; > + reg = <0x1742b000 0x1000>; > + status = "disabled"; > + }; > + > + frame@1742d000 { > + frame-number = <6>; > + interrupts = ; > + reg = <0x1742d000 0x1000>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@17a00000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x17a00000 0x0 0x10000>, > + <0x0 0x17a10000 0x0 0x10000>, > + <0x0 0x17a20000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = , > + , > + ; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = , , > + , ; > + label = "apps_rsc"; > + > + apps_bcm_voter: bcm-voter { > + compatible = "qcom,bcm-voter"; > + }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,qdu1000-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board>; > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,qdu1000-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp1 { > + opp-level = ; > + }; > + > + rpmhpd_opp_min_svs: opp2 { > + opp-level = ; > + }; > + > + rpmhpd_opp_low_svs: opp3 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs: opp4 { > + opp-level = ; > + }; > + > + rpmhpd_opp_svs_l1: opp5 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom: opp6 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l1: opp7 { > + opp-level = ; > + }; > + > + rpmhpd_opp_nom_l2: opp8 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo: opp9 { > + opp-level = ; > + }; > + > + rpmhpd_opp_turbo_l1: opp10 { > + opp-level = ; > + }; > + }; > + }; > + }; > + > + cpufreq_hw: cpufreq@17d90000 { > + compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; > + reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; > + reg-names = "freq-domain0", "freq-domain1"; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #freq-domain-cells = <1>; > + }; > + > + gem_noc: interconnect@19100000 { > + reg = <0x0 0x19100000 0x0 0xB8080>; > + compatible = "qcom,qdu1000-gem-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + }; > + > + arch_timer: timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + , > + ; > + clock-frequency = <19200000>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi > new file mode 100644 > index 000000000000..074fe126e85e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include "qdu1000.dtsi" > + > +&reserved_memory { > + /delete-node/ memory@a0000000; > + /delete-node/ memory@b9600000; > + /delete-node/ memory@c0000000; Please delete memory nodes by referencing the label, so that we don't have to cross-check the files every time. First DT: some_region: something@a0000000 { [...] } Second DT: /delete-node/ &some_region; Konrad > + > + oem_tenx_mem: memory@a0000000 { > + no-map; > + reg = <0x0 0xa0000000 0x0 0x6400000>; > + }; > + > + mpss_diag_buffer_mem: memory@aea00000 { > + no-map; > + reg = <0x0 0xaea00000 0x0 0x6400000>; > + }; > + > + tenx_q6_buffer_mem: memory@b4e00000 { > + no-map; > + reg = <0x0 0xb4e00000 0x0 0x3200000>; > + }; > +};