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Date:   Mon, 21 Nov 2022 12:53:05 +0100
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Subject: Re: [PATCH] arm64: dts: mediatek: mt8195: Fix CPUs capacity-dmips-mhz
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To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>, robh+dt@kernel.org
Cc:     krzysztof.kozlowski+dt@linaro.org, tinghan.shen@mediatek.com,
        seiya.wang@mediatek.com, devicetree@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
References: <20221005093404.33102-1-angelogioacchino.delregno@collabora.com>
From:   Matthias Brugger <matthias.bgg@gmail.com>
In-Reply-To: <20221005093404.33102-1-angelogioacchino.delregno@collabora.com>
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On 05/10/2022 11:34, AngeloGioacchino Del Regno wrote:
> The capacity-dmips-mhz parameter was miscalculated: this SoC runs
> the first (Cortex-A55) cluster at a maximum of 2000MHz and the
> second (Cortex-A78) cluster at a maximum of 3000MHz.
> 
> In order to calculate the right capacity-dmips-mhz, the following
> test was performed:
> 1. CPUFREQ governor was set to 'performance' on both clusters
> 2. Ran dhrystone with 500000000 iterations for 10 times on each cluster
> 3. Calculate the mean result for each cluster
> 4. Calculate DMIPS/MHz: dmips_mhz = dmips_per_second / cpu_mhz
> 5. Scale results to 1024:
>     result_c0 = (dmips_mhz_c0 - min_dmips_mhz(c0, c1)) /
>                 (max_dmips_mhz(c0, c1) - min_dmips_mhz(c0, c1)) * 1024
> 
> The mean results for this SoC are:
> Cluster 0 (LITTLE): 11990400 Dhry/s
> Cluster 1 (BIG): 59809036 Dhry/s
> 
> The calculated scaled results are:
> Cluster 0: 307,934312801831 (rounded to 308)
> Cluster 1: 1024
> 
> Fixes: 37f2582883be ("arm64: dts: Add mediatek SoC mt8195 and evaluation board")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Applied,

Thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 905d1a90b406..0b85b5874a4f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -36,7 +36,7 @@ cpu0: cpu@0 {
>   			enable-method = "psci";
>   			performance-domains = <&performance 0>;
>   			clock-frequency = <1701000000>;
> -			capacity-dmips-mhz = <578>;
> +			capacity-dmips-mhz = <308>;
>   			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
>   			next-level-cache = <&l2_0>;
>   			#cooling-cells = <2>;
> @@ -49,7 +49,7 @@ cpu1: cpu@100 {
>   			enable-method = "psci";
>   			performance-domains = <&performance 0>;
>   			clock-frequency = <1701000000>;
> -			capacity-dmips-mhz = <578>;
> +			capacity-dmips-mhz = <308>;
>   			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
>   			next-level-cache = <&l2_0>;
>   			#cooling-cells = <2>;
> @@ -62,7 +62,7 @@ cpu2: cpu@200 {
>   			enable-method = "psci";
>   			performance-domains = <&performance 0>;
>   			clock-frequency = <1701000000>;
> -			capacity-dmips-mhz = <578>;
> +			capacity-dmips-mhz = <308>;
>   			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
>   			next-level-cache = <&l2_0>;
>   			#cooling-cells = <2>;
> @@ -75,7 +75,7 @@ cpu3: cpu@300 {
>   			enable-method = "psci";
>   			performance-domains = <&performance 0>;
>   			clock-frequency = <1701000000>;
> -			capacity-dmips-mhz = <578>;
> +			capacity-dmips-mhz = <308>;
>   			cpu-idle-states = <&cpu_off_l &cluster_off_l>;
>   			next-level-cache = <&l2_0>;
>   			#cooling-cells = <2>;