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>>> +    u8 vector; >>> + >>> +    while (sev_hv_pending()) { >>> +        asm volatile("cli" : : : "memory"); >>> + >> >> Do we really need to disable interrupts here, #HV exception will be >> dispatched via an interrupt gate in the IDT, so interrupts should be >> implicitly disabled, right ? >>>    panic("Unexpected vector %d\n", vector); >>> +                unreachable(); >>> +            } >>> +        } else { >>> +            common_interrupt(regs, pending_events.vector); >>> +        } >>> + >>> +        asm volatile("sti" : : : "memory"); >> >> Again, why do we need to re-enable interrupts here (in this loop), >> interrupts will get re-enabled in the irqentry_exit() code path ? > > Hi Ashish: >     Thanks for your review.    check_hv_pending() is also called in the > native_irq_enable() to handle some pending interrupt requests after re > -enabling interrupt. For such case, disables irq when handle exception > or interrupt event. > Then probably add the interrupt disable/enable in the caller function like native_irq_enable() which seems logical as check_hv_pending() is always called with interrupts disabled (either via HW or SW) and also interrupt disable/enable seems redundant in check_hv_pending(). Thanks, Ashish