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Date:   Wed, 23 Nov 2022 09:38:48 +0100
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Subject: Re: [PATCH] ARM: at91: fix build for SAMA5D3 w/o L2 cache
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To:     Claudiu.Beznea@microchip.com, clement.leger@bootlin.com,
        regressions@leemhuis.info
Cc:     alexandre.belloni@bootlin.com, linux@armlinux.org.uk,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
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From:   Peter Rosin <peda@axentia.se>
In-Reply-To: <a961e0a1-5373-e2e0-3acb-7ef3cc32d846@microchip.com>
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Hi!

2022-11-23 at 08:19, Claudiu.Beznea@microchip.com wrote:
> On 22.11.2022 19:14, Clément Léger wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Le Tue, 22 Nov 2022 16:13:40 +0100,
>> Thorsten Leemhuis <regressions@leemhuis.info> a écrit :
>>
>>> Hi, this is your Linux kernel regression tracker.
>>>
>>> On 12.11.22 16:40, Peter Rosin wrote:
>>>> The L2 cache is present on the newer SAMA5D2 and SAMA5D4 families, but
>>>> apparently not for the older SAMA5D3. At least not always.
> 
> Peter, what do you mean by "at least not always" here? Are you talking
> about the OUTER_CACHE flag?

I'm not familiar with all options for L2 caching. I was just being cautious
to not exclude the possibility that there could be some variation within
the SAMA5D3 series (I'm on SAMA5D31) or with an external L2 cache or
something such. If there's simply no possible way to have an L2 cache on
any SAMA5D3, feel free to edit that "At least not always" out while you
commit.

>>>>
>>>> Solves a build-time regression with the following symptom:
>>>>
>>>> sama5.c:(.init.text+0x48): undefined reference to `outer_cache'
>>>>
>>>> Fixes: 3b5a7ca7d252 ("ARM: at91: setup outer cache .write_sec() callback if needed")
>>>> Signed-off-by: Peter Rosin <peda@axentia.se>
>>>
>>> Clément Léger and Claudiu Beznea: what's up here? 
> 
> It will be in the next AT91 fixes PR.

Great, thanks!

Cheers,
Peter

*snip*